JPH0322436A - Semiconductor device and manufacture thereof - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Summary] Regarding a semiconductor device and its manufacturing method, especially a protruding electrode (bump, bump electrode) of an LSI chip and its manufacturing method, the lead wire and In order to prevent a reduction in the contact area with the bump electrode and the occurrence of cracks in the insulating film, the purpose is to provide an electrode with a flat surface and a method for manufacturing the same. an insulating film having an aperture exposing the first conductive layer; an electrode in which a recess is formed on the surface of the part;
A step of depositing and forming an insulating film on the surface of the semiconductor device and the first conductive layer, which is connected under pressure to the surface of the electrode that does not include the recess, selectively opening holes in the insulating film. , forming an opening to expose the first conductive layer; forming a base conductive layer so as to extend from the surface of the insulating film to the bottom of the opening; and forming a base conductive layer on the surface of the base conductive layer. patterning a resist layer on a surface that does not include the opening, the opening is located off the center of the surface where the resist layer is not formed, and the resist layer of the base conductive layer is formed by patterning. A step of forming an electrode by electrolytic plating on the surface that does not include the hole, forming a recess on the surface of the electrode above the opening, and connecting the wiring by applying pressure to the upper surface of the electrode that does not include the recess. The present invention includes a method for manufacturing a semiconductor device having a step of:

[Industrial application field]

The present invention relates to a semiconductor device and a method for manufacturing the same, particularly an LSI
The present invention relates to a protruding electrode (bump) of a chip and a method of manufacturing the same.

[Conventional technology]

The connection method using protruding electrodes can increase the number of input/output (I/O) electrodes per unit chip area, speeds up assembly, and is flexible in terms of the shape and dimensions of the mounting base material. It is expected that its utility value will further increase in the future due to increased functionality. For example, with conventional wire bonding technology, each wire was bonded to each electrode one by one. It takes time to bond the wires, the thickness of the mounting base material must be thick enough to withstand the impact of wire bonding, and the wire bonding process also depends on the size of the wire bonder itself. However, when protruding electrodes are used, the inner leads (lead wires) attached to the tape can be bonded by thermocompression etc. at once.
It has the advantage of being more adhesive. In this way, the technological level of connection methods using protruding electrodes has improved, but as a result, the influence of the flatness of the protruding electrode's surface on the connection during mounting cannot be ignored. Research is underway on technology to flatten the surface of

FIG. 3 is a cross-sectional view showing the structure of a general conventional protruding electrode (hereinafter referred to as a bump electrode). In this bump electrode, a passivation N of, for example, silicon nitride (SisN4) is formed on an electrode 32 of, for example, aluminum (An) formed on a mounting base material, for example, a semiconductor substrate 3l.
A contact hole 34 is formed in the (protective insulating film) 33 using a conventional technique, and a bump electrode 36 of, for example, gold (Au) is formed by electroplating via a barrier metal 35. In addition, in the figure, 38 indicates a lead wire.

In this structure, the concave shape of the contact hole 34 is enlarged and transferred onto the surface of the bump electrode 36, and a concave portion 37 is formed in the center.
It has a concave shape.

To explain the reason why such a concave shape is created, a passivation film is formed on the entire surface of the substrate on which the aluminum ξ film is formed, and then the passivation film on the aluminum film is selectively removed to form an aluminum electrode. In the exposure process procedure, it is necessary to consider the alignment margin when forming a mask for removing the passivation film, so it is not possible to remove all the passivation film on the aluminum straw electrode and eliminate the step on the aluminum electrode surface. . Furthermore, when forming the barrier metal on this Al ξ plane, it is also necessary to consider the margin, and the surface on which the bumps are plated will be uneven. In normal plating, the thickness is always uniform starting from the plating surface, so if the bump electrode is formed on an uneven surface like this, the bump electrode will have unevenness even on the upper surface.

[Problem to be solved by the invention]

Therefore, the semiconductor substrate 31 which is a mounting board and the lead wire 38
When connecting via the bump electrode 36 and lead wire 38
Not only does the contact area with the lead wire 38 become smaller, but the pressure applied when bonding the lead wire 38 is locally concentrated as shown by the dashed arrow in the figure, causing a problem of cracks occurring in the passivation layer 33. .

Therefore, the present invention has developed an electrode with a flat surface and a method for manufacturing the same in order to prevent the reduction of the contact area between the lead wire and the bump electrode and the occurrence of cracks in the insulating film due to the formation of recesses on the surface of the bump electrode. The purpose is to provide

[Means to solve the problem]

The above problem is solved by an insulating film that is formed on the surface of a first conductive layer and has an aperture that exposes the first conductive layer, an insulating film that is formed on the insulating crotch, and a bottom surface of the aperture, and that has an aperture that exposes the first conductive layer. A semiconductor device comprising: an electrode in which the aperture is located apart from the aperture; a recess is formed on the surface above the aperture; and a wiring connected under pressure to the electrode surface not including the recess; A step of depositing an insulating film on the surface of the first conductive layer. A step of selectively opening the insulating film to form an opening that exposes the first conductive layer. From the surface of the insulating film. forming a base conductive layer so as to extend on the bottom surface of the opening; and forming a resist layer by patterning on the surface of the base conductive layer that does not include the opening; A step in which the opening is located off the center of the surface where the resist layer is not formed, and an electrode is formed by electrolytic plating on the surface of the underlying conductive layer where the resist layer is not formed, and the electrode is located on the surface where the resist layer is not formed. The problem is solved by a method for manufacturing a semiconductor device that includes a step of forming a recess in the surface, and a step of applying pressure to connect wiring to the upper surface of the electrode that does not include the recess.

[Effect]

FIG. 1 is a diagram of an embodiment of the present invention, in which (a) is a plan view, and (b) is a sectional view taken along the line xx' in (a).
1 is a mounting base material, for example a semiconductor substrate; 13 is a first conductive layer; 14 is an insulating film; 15 is an opening; 16 is a base conductive layer;
17 is an electrode, and 21 is a wiring. In this structure, a small opening 15 is formed in the insulating film 14 on the first conductive layer 13 at a position offset from the center of the first conductive layer 13, as shown in FIG. Furthermore, the base conductive layer 16
The electrode 17 is formed by plating through the wafer.

That is, in the present invention, as shown in FIG.
The insulating film 14 on the conductive layer 13 is left wide and the electrode 17 is formed by plating.When plated, the base is flat, so the electrode 17 transfers that flatness and has a flat surface. This will solve the conventional problems.

〔Example〕

Hereinafter, the present invention will be specifically explained with reference to illustrated embodiments.

Referring again to FIG. 1, the first conductive layer 13 formed on the mounting base material, for example, the semiconductor substrate 11, has an overhanging portion in which the opening forming portion protrudes from the main body portion of the first conductive layer. 13a, and an opening 15 is formed above the overhanging portion 13a, which is the opening-shaped portion of the insulating film 14 covering the first conductive layer 13. . In this way, the opening 15 is made smaller than the conventional one with respect to the first conductive layer 13 and at a position shifted from the center of the first conductive layer 13. Then, a base conductive layer 16 that has high adhesion to the first conductive layer 13 and plays the role of an electrode in electrolytic plating is formed, a resist is applied to the entire surface, and an electrode is formed by plating using known or lithographic techniques. form a pattern to The size of the electrode 17 must be large enough to ensure sufficient adhesion with the lead wire, and the size of the first conductive electrode 17 must be large enough to ensure sufficient adhesion with the lead wire. layer 1
It is formed smaller than 3. After removing the resist, the underlying conductive layer 16 is etched to complete the electrode formation.

When connecting the wiring 21, the wiring 21 is connected to the wide flat surface of the electrode 17 over the entire surface, and the wiring 21 is not in contact with the recess 18 formed in the electrode above the opening 15.

Therefore, the force applied to the wiring 21 when bonding the wiring 21 is distributed evenly over almost the entire electrode 17, and the force applied to the insulating film 14 is also distributed evenly, so that cracks do not occur in the insulating film 14 as in the conventional example. is prevented.

In a modified example of the present invention, the electrode 17 is formed so as to extend to the extending portion 17a of the electrode shown by the broken line in FIG. 21a, and the wiring 21 is connected to the electrode 17.
The adhesive is bonded as shown by the broken line in the plan view of FIG. 1(a) so as not to straddle the recess 18. By doing so, the wiring 2l comes into contact with the flat surface of the electrode 17 over the entire length of the wiring 21, thereby avoiding the problems of the conventional example.

A method of forming an embodiment of the invention will now be described with reference to FIG.

See Figure 2(a): ? An insulating film 12, such as a SiO2 film 12, is formed on the conductor substrate 11 to a thickness of 1000 nm by a known method such as thermal oxidation, and then M, for example, is evaporated to a thickness of 1 Ilm thereon. A first conductive layer 13 is formed by patterning into the shape shown in the figure, and is further formed of, for example, Si3Na w! One edge 11A14 is shaped to a thickness of 1 pm to 1.5.1110 mm.

See Figure 2 (b): Openings 1 for conduction are formed in the insulating film 14 by a normal photo process.
Shape 5. The position and shape of the opening 15 are shown in Figure 1 (
The first conductive layer 1 is the same as shown in the top view in a).
It is located off the center of 3.

Refer to FIG. 2(C): A titanium (Ti) film and a palladium (Pd) film each having a thickness of 3000 A are deposited on the entire surface by sputtering to form a base conductive layer 16 for an electrode. Note that the conductive base 1116 serves not only as a barrier metal layer but also as an electrode during plating.

11 l2 See FIG. 2(d): After coating a resist layer 19 for forming an electrode on the underlying conductive layer l6 to a thickness of, for example, 30 mm, corresponding to the height of the electrode to be formed, the resist layer 19 is opened. A predetermined pattern is printed and developed to include the holes 15.

Refer to FIG. 2(e): By applying gold (Au) plating using the resist layer 19 as a mask, an electrode 17 made of ^U is formed.

Refer to FIG. 2(f): Finally, the resist layer 19 is dissolved and removed, and then the electrode 1
7 as a mask, the base conductive layer 16 is etched to complete the semiconductor device with electrodes.

By the way, several inventions that aim at the problems to be solved by the present invention have been made public.

One of them is Japanese Unexamined Patent Publication No. 62-94962, and the invention disclosed therein, as shown in FIG. The first wiring layer 43 provided on 42 and the first wiring layer 4
a second insulating film 44 that selectively has an opening 45 on the second insulating film 44 and covers the entire surface other than the opening 45; A pad 46 is electrically connected to the layer 43, and a second wiring layer (
(not shown), and a third insulating film having a thickness that is approximately the same as the depth of the four parts formed in the pad 46 due to the presence of the opening 45, and covers the peripheral part of the pad 46 but does not cover the central part. 47 and a bump 50 provided on the pad 46 including the peripheral portion covered with the third insulating film 47. In the figure, 48 is a contact metal layer, and 49 is a barrier metal layer.

In this known example, the opening 45 is filled with a third insulating film 47 in order to flatten the surface of the bump electrode.

Therefore, the process of opening the opening 45 for conduction is performed twice, which increases the number of processes, whereas in the present invention, the process of forming the insulator 11l14 corresponding to the second insulating film 44 of the known example is The manufacturing method is simplified because it can be the same as the example.

13 l4 Furthermore, in the known example, one more layer of pads 46 is required on the first wiring layer 43, but in the invention of the present application, one layer of the first conductive layer 13 is sufficient as in the conventional example. Therefore, it is easy to manufacture.

As mentioned above, this known example involves an increased number of steps, but the method of the present invention has the advantage of being easier to implement.

Another known example is JP-A-62-2068.
5. Referring to FIG. 5, the invention disclosed in this publication is a wiring layer 52 provided on a substrate 51, a protective insulating film 53 provided on the wiring layer 52, and a conductor provided thereon. In a semiconductor device including a communication hole 54 and a bump electrode 57 electrically connected to the wiring layer 52 through the conduction hole 54, the bump electrode 57 is connected to the wiring layer or the wiring layer in the portion of the conduction hole 54. 52 and provided on the lead wiring layer 59 provided on the insulating film 53.
This lead wiring layer 59 consists of a base conductive film 55 and an uppermost layer 60.
It is determined by

In this known example, the uppermost part of the lead-out wiring layer is required, but in the present invention, since the electrode 17 itself is used as a mask, the number of steps is small and manufacturing is easy.

Further, in the known example, the wiring 11 is drawn out from the conduction hole 54.
Since the i59 is drawn out, an extra area is required for the conduction hole 54, which is contrary to the integration of semiconductor devices, but in the present invention, the dimensions and position of the first conductive layer 13 are the same as in the conventional Since the opening for conduction is only made smaller, an extra area is not required as in the known example.

Note that when the electrode 17 is formed by a method other than electrolytic plating, the base conductive layer 16 forming the plating electrode is not required.

〔Effect of the invention〕

As described above, according to the present invention, the following effects can be achieved, the mounting can be made even more reliable, and this greatly contributes to improving the reliability of semiconductor devices.

15 16 (a) The surface of the electrode 17 is flat.

O) Wiring 2 when connecting to mounting base material etc. via wiring 21
Since the contact area with 1 can be secured, a stable connection can be achieved.

(C) When the electrode 17 is made of gold, its adhesion to the insulating film 14 is better than its adhesion to the first conductive layer 13;
Adhesion is improved by increasing the area of contact with the insulating film 14.

(d) When connecting the wiring 21, stress is uniformly absorbed over a wide area, so that cranks are less likely to occur in the insulating film 14.

[Brief Description of the Drawings] Figure 1 is a diagram of an embodiment of the present invention, in which (a) is a plan view, (b) is a sectional view, and Figures 2 (a) to (f) are diagrams of an embodiment of the present invention. FIG. 3 is a cross-sectional view of a conventional bump electrode, and FIGS. 4 and 5 are cross-sectional views of known examples. In the figure, 11 is a semiconductor substrate (mounting base material), 12 is an insulating film, 13 is a first conductive layer, 13a is an overhanging part, l4 is an insulating film, 15 is an opening, 16 is a base conductive layer, 17 is a Reference numeral 17a indicates an extended portion of the electrode, 18 indicates a recessed portion, 19 indicates a resist layer, 2l indicates a wiring, and 21a indicates an extended portion of the wiring.

Claims (2)

[Claims] (1) formed on the surface of the first conductive layer (13);
an insulating film (14) having an opening (15) that exposes a conductive layer (13); an electrode (17) in which the aperture (15) is located and a recess (18) formed on the surface above the aperture (15); and an electrode (17) that does not include the recess (18). A semiconductor device having a wiring (21) connected to the surface under pressure. (2) An insulating film (14) is formed on the surface of the first conductive layer (13).
A step of selectively opening the insulating film (14) to form an opening (15) exposing the first conductive layer (13). ) Forming a base conductive layer (16) so as to extend from the surface to the bottom of the opening (15); and not including the opening (15) on the surface of the base conductive layer (16). A step of patterning a resist layer (19) on the surface and positioning the opening (15) off the center of the surface where the resist layer (19) is not formed; An electrode (17) is formed by electrolytic plating on the surface where the resist layer (19) is not formed, and an electrode (17) is formed on the surface where the resist layer (19) is not formed.
15) Forming a recess (18) on the surface of the electrode (17) above, and connecting the wiring (21) by applying pressure to the upper surface of the electrode (17) that does not include the recess (18). A method for manufacturing a semiconductor device, comprising the steps of: