JPH0322446U - - Google Patents
Info
- Publication number
- JPH0322446U JPH0322446U JP8218289U JP8218289U JPH0322446U JP H0322446 U JPH0322446 U JP H0322446U JP 8218289 U JP8218289 U JP 8218289U JP 8218289 U JP8218289 U JP 8218289U JP H0322446 U JPH0322446 U JP H0322446U
- Authority
- JP
- Japan
- Prior art keywords
- clock signal
- output
- input
- logical sum
- calculating means
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000001514 detection method Methods 0.000 claims description 3
- 238000003708 edge detection Methods 0.000 claims 2
- 230000008929 regeneration Effects 0.000 claims 2
- 238000011069 regeneration method Methods 0.000 claims 2
- 238000010586 diagram Methods 0.000 description 4
Landscapes
- Synchronisation In Digital Transmission Systems (AREA)
Description
第１図はこの考案の一実施例の構成を示すブロ
ツク図。第２図はこの考案の一実施例の作用の説
明に供するタイミング図。第３図はこの考案の他
の実施例の構成を示すブロツク図。第４図は従来
例の構成を示すブロツク図。
１……立下がり検出回路、２……オアゲート、
３……カウンタ、４……Ｍ／４検出器、５……Ｍ
／２検出器、６……3/4Ｍ検出器、７……Ｍ検出
器、８および９……オアゲート、１０……フリツ
プフロツプ、１１……オアゲート、１２，１３お
よび１４……初期値設定器、１５……カウンタ、
１６……最小値検出器、１７……最大値検出器、
１８……フリツプフロツプ、１９……コントロー
ル回路、２０……マルチプレクサ、２１……ラツ
チ回路。
FIG. 1 is a block diagram showing the configuration of an embodiment of this invention. FIG. 2 is a timing diagram for explaining the operation of one embodiment of this invention. FIG. 3 is a block diagram showing the configuration of another embodiment of this invention. FIG. 4 is a block diagram showing the configuration of a conventional example. 1...Falling detection circuit, 2...OR gate,
3...Counter, 4...M/4 detector, 5...M
/2 detector, 6...3/4M detector, 7...M detector, 8 and 9...OR gate, 10...flip-flop, 11...OR gate, 12, 13 and 14...initial value setter, 15...Counter,
16... Minimum value detector, 17... Maximum value detector,
18...Flip-flop, 19...Control circuit, 20...Multiplexer, 21...Latch circuit.
Claims (1)
エツジ検出手段と、内部クロツク信号をカウント
するカウンタと、カウンタの計数値が［（再生ク
ロツク信号周期×２）／内部クロツク信号周期］
の1/4，1/2，3/4，１倍に達したことを夫々検出
する第１、第２、第３および第４の検出器と、第
１および第３の検出器の検出出力を入力とする第
１の論理和演算手段と、第２および第４の検出器
の検出出力を入力とする第２の論理和演算手段と
、第１の論理和演算手段を出力を一方の入力とし
、かつ第２の論理和演算手段の出力を他方の入力
としてセツト、リセツトされるフリツプフロツプ
と、前記エツジ検出手段の出力および第４の検出
器の検出出力を入力とし、かつ出力で前記カウン
タをリセツトする第３の論理和演算手段とを備え
、前記フリツプフロツプの出力を再生クロツク信
号とすることを特徴とするクロツク信号再生回路
。 An edge detection means for detecting one edge of input serial data, a counter for counting an internal clock signal, and a count value of the counter is [(regenerated clock signal period x 2)/internal clock signal period]
first, second, third, and fourth detectors that respectively detect that the amount has reached 1/4, 1/2, 3/4, and 1 times of a first logical sum calculating means which receives as input, a second logical sum calculating means which receives the detection outputs of the second and fourth detectors as input, and a second logical sum calculating means which receives the output of the first logical sum calculating means as one input. and a flip-flop which is set and reset with the output of the second OR calculation means as the other input, the output of the edge detection means and the detection output of the fourth detector as inputs, and the output of the flip-flop which is set and reset. 1. A clock signal regeneration circuit, comprising: third OR operation means for resetting the clock signal, and the output of said flip-flop is used as a regeneration clock signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1989082182U JPH0724833Y2 (en) | 1989-07-14 | 1989-07-14 | Clock signal regeneration circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1989082182U JPH0724833Y2 (en) | 1989-07-14 | 1989-07-14 | Clock signal regeneration circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0322446U true JPH0322446U (en) | 1991-03-07 |
| JPH0724833Y2 JPH0724833Y2 (en) | 1995-06-05 |
Family
ID=31628762
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1989082182U Expired - Lifetime JPH0724833Y2 (en) | 1989-07-14 | 1989-07-14 | Clock signal regeneration circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0724833Y2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06343211A (en) * | 1993-05-31 | 1994-12-13 | Nippon Telegr & Teleph Corp <Ntt> | Support pole for telephone pole reinforcement and its mounting method |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5610822A (en) * | 1979-07-03 | 1981-02-03 | Gelenkwellenbau Gmbh | Universal joint |
-
1989
- 1989-07-14 JP JP1989082182U patent/JPH0724833Y2/en not_active Expired - Lifetime
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5610822A (en) * | 1979-07-03 | 1981-02-03 | Gelenkwellenbau Gmbh | Universal joint |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06343211A (en) * | 1993-05-31 | 1994-12-13 | Nippon Telegr & Teleph Corp <Ntt> | Support pole for telephone pole reinforcement and its mounting method |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0724833Y2 (en) | 1995-06-05 |
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