JPH0449883U

JPH0449883U -

Info

Publication number: JPH0449883U
Application number: JP9112290U
Authority: JP
Priority date: 1990-08-30
Filing date: 1990-08-30
Publication date: 1992-04-27

Description

[Brief explanation of the drawing]

第１図は本考案の一実施例の回路図、第２図は
第１図の実施例のタイムチヤート、第３図はＬＳ
ＩテスタによるＬＳＩの試験の方法の説明図、第
４図は従来のマルチクロツク回路の回路図、第５
図は第４図のマルチクロツク回路の動作のタイム
チヤート、第６図は第４図の回路のメモリに格納
されているデータの一例を示す図である。１１……アツプカウンタ、１２……一致検出回
路、１３……データラツチ、１５……メモリ、１
６，１８……遅延素子、１７……オア回路、１９
……エツジ数カウンタ、２０……エツジ数メモリ
、２１……エツジ数検出回路。 Fig. 1 is a circuit diagram of an embodiment of the present invention, Fig. 2 is a time chart of the embodiment of Fig. 1, and Fig. 3 is a LS
An explanatory diagram of the LSI testing method using an I tester. Figure 4 is a circuit diagram of a conventional multi-clock circuit. Figure 5
4 is a time chart of the operation of the multi-clock circuit shown in FIG. 4, and FIG. 6 is a diagram showing an example of data stored in the memory of the circuit shown in FIG. 4. 11... Up counter, 12... Coincidence detection circuit, 13... Data latch, 15... Memory, 1
6, 18... Delay element, 17... OR circuit, 19
...Edge number counter, 20...Edge number memory, 21...Edge number detection circuit.

Claims

[Claims for Utility Model Registration] An up counter 11 that counts up every clock input, a memory 15 that stores the number of multi-clocks set in one rate signal, and latches the data stored in the memory 15. A data latch 13, a coincidence detection circuit 12 that detects coincidence between the output of the up counter 11 and the output of the data latch 13 and outputs an edge signal, and a logical sum of the edge signal and the rate signal through delay elements 16 and 18. In a multi-clock generation circuit of an LSI tester that generates a plurality of edge signals in one rate signal and includes an OR circuit 17 input to the data latch 13, the number of edge signals of the coincidence detection circuit 12 is counted and counted up. , an edge number counter 19 that outputs the counted number to the memory 15 as an address; an edge number memory 20 that stores the number of edges to be output according to the length of the rate signal; and output data of the edge number counter 19. and the output data of the edge number memory 20 are input, detect a match, and when they match, input a count control signal to the edge number counter 19 to hold the output data.
A multi-clock generation circuit for an LSI tester, comprising: