JPH0322447U - - Google Patents

Description

[Brief explanation of the drawing]

Figure 1 shows an embodiment of this invention;
FIG. 3 is a diagram showing the operation timing of an embodiment of this invention, FIG. 3 is a diagram showing an example of a conventional data receiving device,
FIG. 4 is a diagram showing the operation timing of an example of a conventional data receiving device. In the figure, 1...data transmitting device, 2...receiver, 3...data holding section, 4...data receiving device, 5...sample timing generation circuit, 6...
...data integration circuit, 7...determination circuit. Note that the same reference numerals in each figure indicate the same or equivalent parts.

Claims (1)

[Scope of utility model registration request] Receives data signals with meanings such as numerical values, symbols, codes, characters, etc. output from a data transmitter and write signals output from the data transmitter in synchronization with this data signal, and shapes these signal waveforms. In a data receiving device consisting of a receiver and a data holding unit that holds the data signal shaped by the receiver in synchronization with the write signal, a clock signal is generated in the data receiving device in synchronization with the write signal. a sample timing generation circuit for sampling the data signal in synchronization with this clock signal to obtain an integral value, and a data integrating circuit for determining whether the data is a logic "1" or "0" from this integral value. By adding a determination circuit for determining the data, even if sporadic noise is superimposed on the data signal sent from the data transmitting device, it is possible to obtain a correct data signal to the data receiving device. Characteristic data receiving device.