JPH0322536A - Resin-sealed semiconductor device - Google Patents
Resin-sealed semiconductor deviceInfo
- Publication number
- JPH0322536A JPH0322536A JP15590589A JP15590589A JPH0322536A JP H0322536 A JPH0322536 A JP H0322536A JP 15590589 A JP15590589 A JP 15590589A JP 15590589 A JP15590589 A JP 15590589A JP H0322536 A JPH0322536 A JP H0322536A
- Authority
- JP
- Japan
- Prior art keywords
- resin
- wiring
- semiconductor device
- end parts
- sealed
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 13
- 239000011347 resin Substances 0.000 claims abstract description 10
- 229920005989 resin Polymers 0.000 claims abstract description 10
- 239000000758 substrate Substances 0.000 claims abstract description 6
- 230000001681 protective effect Effects 0.000 abstract description 4
- 239000011229 interlayer Substances 0.000 abstract description 3
- 238000000034 method Methods 0.000 abstract description 3
- 238000005530 etching Methods 0.000 abstract description 2
- 239000010410 layer Substances 0.000 abstract description 2
- 239000000463 material Substances 0.000 abstract description 2
- 230000003449 preventive effect Effects 0.000 abstract 1
- 238000007789 sealing Methods 0.000 description 7
- 230000035882 stress Effects 0.000 description 5
- 101700004678 SLIT3 Proteins 0.000 description 2
- 102100027339 Slit homolog 3 protein Human genes 0.000 description 2
- 239000000919 ceramic Substances 0.000 description 1
- 239000012141 concentrate Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 230000035939 shock Effects 0.000 description 1
- 230000008646 thermal stress Effects 0.000 description 1
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
（産業上の利用分野）
本発明は樹脂封止型半導体装置における配線の構造に関
するものである。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a wiring structure in a resin-sealed semiconductor device.
（従来の技術）
ＩＣチップを封止する方法として、セラミック封止等の
・・−メチック封止や樹脂体を用いた樹脂封止があるが
、ローコスト等のため後者が主流となっている。近年で
はＩＣの集積化が進み、チッグサイズの大型化金もたら
しておシ、樹脂封止型を用いた場合、温度サイクル等の
熱衝撃によるストレスがＩＣチップに悪影響を及し、具
体的にはＡｔスライド等を発生させていた。(Prior Art) Methods for sealing IC chips include ceramic sealing, etc. -metic sealing, and resin sealing using a resin body, but the latter is the mainstream due to its low cost. In recent years, the integration of ICs has progressed, leading to larger chip sizes, and when resin-sealed types are used, stress due to thermal shocks such as temperature cycles has a negative impact on IC chips, and specifically, At This caused slides, etc.
これを解決するため、種々の提案がなされている。第２
図に、その１例を示す。第２図（Ａ）は平面図であシ、
第２図（Ｂ）は、第２図（Ａ）のＡ − Ａ’の断面図
である。Various proposals have been made to solve this problem. Second
An example is shown in the figure. Figure 2 (A) is a plan view;
FIG. 2(B) is a sectional view taken along line A-A' in FIG. 2(A).
半導体基板１上に絶Ｒ膜４を介して配線２が敷設されて
いる。この配ｆＲ２には、配線２の延在方向に沿ってス
リソト３が形成されて卦シ、保護膜５を介して樹脂封止
がなされる。配線２にスリソト３を設けることによシ配
線に集中する封脂応カ金分散し、Ａｔスライド現象を防
止しようとするものである。A wiring 2 is laid on a semiconductor substrate 1 with an insulated film 4 interposed therebetween. A slit 3 is formed along the extending direction of the wiring 2 in this distribution fR2, and resin sealing is performed via a protective film 5. By providing the slit 3 on the wiring 2, the sealing metal that concentrates on the wiring is dispersed and the At slide phenomenon is prevented.
（発明が解決しようとする課題）
しかしながら、前述の様な構造は、応力が小さいものに
ついては有効であるが、大型化したＩＣにかいては樹脂
応力も大きく、実質的に配線幅金小さくする前述の構成
では完全にＡｔスライド現象を防ぐことはできるもので
はなかった。(Problem to be Solved by the Invention) However, although the above-mentioned structure is effective for devices with low stress, the resin stress is large for large-sized ICs, and the wiring width is essentially reduced. With the above-mentioned configuration, it was not possible to completely prevent the At slide phenomenon.
（課題金解決するための手段）
上述の問題点に鑑み、本発明の構成は、半導体の素子領
域を接続する配線層の断面端部にテー・ぐ形状を設けた
ものとする。(Means for Solving the Problems) In view of the above-mentioned problems, the configuration of the present invention is such that a tapered shape is provided at the cross-sectional end of a wiring layer that connects semiconductor element regions.
（作用）
本発明は、上記構戒としたため樹脂の熱応力がテー・ぐ
部に沿って逃げるため、配線に対し横方向からの応力が
大幅に減少する作用がある。(Function) Since the present invention adopts the above-mentioned precautions, the thermal stress of the resin escapes along the tapered portion, so that the stress applied to the wiring from the lateral direction is significantly reduced.
（実施例）
本発明の一実施例金第１図に示す。半導体基板１上に厚
みが７０００〜ｓｏｏｏＸの層間絶縁膜４全形成する。(Example) An example of the present invention is shown in FIG. An interlayer insulating film 4 having a thickness of 7,000 to sooox is entirely formed on a semiconductor substrate 1.
次に、この層間絶縁膜２上に厚みが１μｍ程度の所望の
Ａｔ配線／ぐターン６を形成した後、その端部がテーパ
形状を有するようにエッチング套処理金施す．このテー
／−，Ｏ角度は、６０度以下とすることが望１しい。Next, a desired At wiring/gutter 6 having a thickness of about 1 μm is formed on the interlayer insulating film 2, and then an etching process is performed so that the end thereof has a tapered shape. It is desirable that this T/-, O angle be 60 degrees or less.
その後、５０００〜８０００Ｘ厚の保護膜７金形成し、
樹脂材８によシ封止される。After that, a protective film of 7 gold with a thickness of 5000 to 8000X was formed,
It is sealed with a resin material 8.
（効果）
以上、詳細に説明したように本発明の様な配線／ぐター
ンとすることで、通常発生する横方向からの樹脂応力は
テーパに沿って逃がすことができる。(Effects) As described above in detail, by using the wiring/gutturn as in the present invention, resin stress that normally occurs in the lateral direction can be released along the taper.
又、配線幅も実質的に同一であるため、その他の原因に
よるＡｔ配線の断線防止力も従来のスリソ１・を有する
配線パターンに比べ向上する。Further, since the wiring width is substantially the same, the ability to prevent At wiring from breaking due to other causes is improved compared to the conventional wiring pattern having slits 1.
第１図は、本発明にかかる樹脂封止型半導体装置の断面
図である。第２図（Ａ）は、従来技術にかかる樹脂封止
型半導体装置の平面図である。第２図（Ｂ）は、第２図
（Ａ）にかけるＡ − Ａ’の断面図である。
１・・・半導体基板、２，６・・・配線、３・・・スリ
ット、４・・・絶縁膜、５，７・・・保護膜、８・・・
封止樹脂。FIG. 1 is a sectional view of a resin-sealed semiconductor device according to the present invention. FIG. 2(A) is a plan view of a resin-sealed semiconductor device according to the prior art. FIG. 2(B) is a sectional view taken along line A-A' in FIG. 2(A). DESCRIPTION OF SYMBOLS 1... Semiconductor substrate, 2, 6... Wiring, 3... Slit, 4... Insulating film, 5, 7... Protective film, 8...
Sealing resin.
Claims (1)
子領域を接続する配線層とを有し、前記基板を樹脂体に
て封止した半導体装置において、前記配線層は断面テー
パー形状であることを特徴とする樹脂封止型半導体装置
。In a semiconductor device having an element region formed on one principal surface of a semiconductor substrate and a wiring layer connecting the element region, and in which the substrate is sealed with a resin body, the wiring layer has a tapered cross-section. A resin-sealed semiconductor device characterized by the following.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15590589A JPH0322536A (en) | 1989-06-20 | 1989-06-20 | Resin-sealed semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15590589A JPH0322536A (en) | 1989-06-20 | 1989-06-20 | Resin-sealed semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0322536A true JPH0322536A (en) | 1991-01-30 |
Family
ID=15616079
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15590589A Pending JPH0322536A (en) | 1989-06-20 | 1989-06-20 | Resin-sealed semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0322536A (en) |
-
1989
- 1989-06-20 JP JP15590589A patent/JPH0322536A/en active Pending
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPH06232256A (en) | Method for forming crack stop of semiconductor device and semiconductor device | |
| GB2184600A (en) | Bonding pad interconnection structure | |
| IT8322982A1 (en) | ELECTRONIC DEVICE INCLUDING A PLATE INCLUDING A SUBSTRATE AND AN ELECTRICAL CONNECTION STRUCTURE FORMED ON A GREATER SURFACE OF THE SUBSTRATE AND CONSISTING OF AN ELECTRICALLY INSULATING FILM AND A METALLIC CONNECTION LAYER | |
| US6500764B1 (en) | Method for thinning a semiconductor substrate | |
| CA2075462C (en) | Bump structure and method for bonding to a semi-conductor device | |
| JPH0322536A (en) | Resin-sealed semiconductor device | |
| US5153700A (en) | Crystal-etched matching faces on semiconductor chip and supporting semiconductor substrate | |
| JPS63232447A (en) | Semiconductor device | |
| JP2844633B2 (en) | Semiconductor die for plastic encapsulation with adhesion promoter | |
| JPH0322535A (en) | Resin sealed semiconductor device | |
| JPS60235446A (en) | Semiconductor device and manufacture thereof | |
| JPH01309351A (en) | Semiconductor chip | |
| JPH02121333A (en) | Semiconductor device and its manufacture | |
| JP2789467B2 (en) | Semiconductor device | |
| JPH03136351A (en) | Semiconductor integrated circuit | |
| KR920007191B1 (en) | Semiconductor device manufacturing method | |
| JPS63283042A (en) | Semiconductor element | |
| KR100206916B1 (en) | Pad protecting method of semiconductor chip against di water | |
| JPS58219741A (en) | Semiconductor device | |
| JPH0230131A (en) | Semiconductor device | |
| JPH04286341A (en) | Semiconductor device | |
| JPH04171835A (en) | Resin sealed semiconductor device | |
| JPS6294964A (en) | Bump construction | |
| KR19980057588A (en) | Chip crack protection | |
| JPH01270308A (en) | Semiconductor chip |