JPH0322537A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH0322537A JPH0322537A JP15897289A JP15897289A JPH0322537A JP H0322537 A JPH0322537 A JP H0322537A JP 15897289 A JP15897289 A JP 15897289A JP 15897289 A JP15897289 A JP 15897289A JP H0322537 A JPH0322537 A JP H0322537A
- Authority
- JP
- Japan
- Prior art keywords
- film
- layer
- conductive material
- wiring
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は、2層以上の多層配線からなる半導体装置の
製造方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to a method of manufacturing a semiconductor device comprising multilayer wiring of two or more layers.
第2図(a)〜(d)は従来の1層配線以降の半導体装
置の製造フローを示す断面図である。第2図において、
1は半導体基板、2はこの半導体基板1上に形成された
ウェル、3ばこのウェル2に拡散された拡散層、4は素
子分離のためのフィールド酸化膜、5はゲー1・酸化膜
、6はこのゲー1・酸化膜5上に形成されたゲー1・、
7はスムーズコ1・、8は第1層のアルミ配線、10は
層間絶縁膜、11は第2層のアルミ配線である。FIGS. 2(a) to 2(d) are cross-sectional views showing the manufacturing flow of a conventional semiconductor device after one-layer wiring. In Figure 2,
1 is a semiconductor substrate, 2 is a well formed on this semiconductor substrate 1, 3 is a diffusion layer diffused into the well 2, 4 is a field oxide film for element isolation, 5 is a gate 1 oxide film, 6 is the gate 1 formed on the gate 1 oxide film 5,
7 is a smooth coater 1.8 is a first layer of aluminum wiring, 10 is an interlayer insulating film, and 11 is a second layer of aluminum wiring.
次に製造工程について説明する。Next, the manufacturing process will be explained.
まず、第2図(a)に示すように、半導体基板1にウエ
ル2,拡散層3,フィールド酸化膜4,ゲ1・酸化膜5
,ゲー1・6が形成され、その後全面にスムースコー1
・7が形成され、このスムースコ1− 7の所定位置に
開口部を形成した後、第1層のアルミ配線8を形成する
。その後、第2図(b)に示すように、プラズ7 C
V D (Chemical VaporDeposi
tion)法により酸化膜あるいは窒化膜からなる層間
絶縁膜10を形成し、次いで第1図(c)(1)
(2)
に示すように、フォ1・レジス1−(図示せず)をバタ
ーニングし、CHF3などのガスを用いた乾式エッチン
グによりスルーホールを形成し、最後に2層目のア/L
ミをスバツタ法により形成した後、フォl・レジス1・
(図示せず)をパターニングし、これをマスクにして塩
素系のガスを用いた乾式エッチング法によりエッチング
を行い、第2層のアルミ配線11を形成する。First, as shown in FIG. 2(a), a semiconductor substrate 1 is provided with a well 2, a diffusion layer 3, a field oxide film 4, a gate 1 and an oxide film 5.
, Game 1 and 6 are formed, and then smooth coat 1 is formed on the entire surface.
- 7 is formed, and after forming an opening at a predetermined position of this smoothcoat 1-7, the first layer of aluminum wiring 8 is formed. After that, as shown in FIG. 2(b), Plas7C
V D (Chemical Vapor Deposit)
An interlayer insulating film 10 made of an oxide film or a nitride film is formed by the oxide film or nitride film, and then, as shown in FIG. Then, through-holes are formed by dry etching using a gas such as CHF3, and finally the second layer A/L is formed.
After forming the resist layer 1 by the subvert method,
(not shown) is patterned, and using this as a mask, etching is performed by a dry etching method using chlorine-based gas to form the second layer of aluminum wiring 11.
従来の半導体装置のア)L妃配線は、以上のようにして
形成されるので、微細化が進むにつれてスルーホール開
口面積が小さくなると、ス/L−ポル部の第2層のアル
ミ配線11のカバレッジが悪くなったり、また、層間絶
縁膜10の異方性エッチングの際、ポリマ重含膜がスル
−ホー/Lの開1]部や側壁に付着し、第1層,第2層
のアルミ配線8,11間のオーミック性が悪くなるなど
の問題点があった。A) The L-pin wiring of the conventional semiconductor device is formed as described above, so as the through-hole opening area becomes smaller as the miniaturization progresses, the second layer aluminum wiring 11 in the S/L-Pole portion becomes smaller. In addition, during anisotropic etching of the interlayer insulating film 10, the polymer-heavy film may adhere to the opening 1] of the through-hole/L and the side walls, causing the aluminum of the first and second layers to deteriorate. There were problems such as poor ohmic properties between the wirings 8 and 11.
乙の発明は、上記のような問題点を解消−4るt−めに
なされたもので、ボリマ重合膜が形成されず、アルξ配
線間の4−くツク性の良好な半導体装置の製造方法を得
る乙とを目的とする。The invention of B was made to solve the above-mentioned problems, and it is possible to manufacture a semiconductor device that does not form a polymeric film and has good 4-connectivity between aluminum wirings. The purpose is to obtain a method.
乙の発明:ζ係る半導体装置の製造方法は、第1層のア
ルミ配線上{こ導電性材料からなる膜を形成し、この膜
を介して第2層のアルミ配線を形成するものである。Invention B: ζ The method for manufacturing a semiconductor device is to form a film made of a conductive material on a first layer of aluminum wiring, and form a second layer of aluminum wiring via this film.
この発明においては、第1層,第2層のアノL8配線間
に導電性材料からなる膜を形成することにより、アノし
く配線間のオーミ・ソク性が良好となる。In this invention, by forming a film made of a conductive material between the ANO L8 wirings in the first layer and the second layer, the ohm-isolation property between the ANO wirings is improved.
以下、乙の発明の一実施例を図面について説明する。 An embodiment of the invention of B will be described below with reference to the drawings.
第1図(a)〜(e)はこの発明による半導体装置の製
造フローを示す断面図であり、第2図と同一符号は同一
のものを示す。FIGS. 1(a) to 1(e) are cross-sectional views showing the manufacturing flow of a semiconductor device according to the present invention, and the same reference numerals as in FIG. 2 indicate the same parts.
まず、第1図(a)に示すように、従来例と同様にして
第1層のアi+.i:配線8を形成した後、第1図(b
)に示すよう(こ、′l″i,W,Cuなどの金属(3
)
(4)
あるいはMoS ltp WS l2, T i S
i2などのシリサイドからなる導電性の膜を全面にスバ
ッタ法により形成し、写真製版,エッチノグを行いバタ
ーニングされた導電性材料からなる膜9を形成する。次
に第1図(c)に示すように、プラズマCVD法により
、酸化膜あるいは窒化膜からなる層間絶縁膜10を形成
する。続いて第1図(d)に示すように、層間絶縁膜1
0上に、図示されていtrいフォ1・レジスl・の塗布
を行った後、層同絶縁膜10と選択比が1となるような
エッチング法により、導電性材料からなる膜9の表面が
露出するまでエッチバックを行い、さらに拡散層3との
コノタク1・部などの段差部に残っているフォ1・レジ
ス1・の除去を行う。最後1ζ第1図(e)1ζ示ずよ
うに、第2層のアルミをスバッタ法により形成し、フォ
1・レジス1・(図示せず)をバターニノグし、乾式エ
ッチング法によりエッチノグを行い、第2層のアルく配
線11を形成する。First, as shown in FIG. 1(a), the first layer i+. i: After forming the wiring 8, as shown in FIG.
), metals (3) such as
) (4) Or MoS ltp WS l2, T i S
A conductive film made of silicide such as i2 is formed on the entire surface by a sputtering method, and photolithography and etching are performed to form a patterned film 9 made of a conductive material. Next, as shown in FIG. 1(c), an interlayer insulating film 10 made of an oxide film or a nitride film is formed by plasma CVD. Subsequently, as shown in FIG. 1(d), an interlayer insulating film 1 is formed.
After applying a photoresist (not shown) on the layer 0, the surface of the film 9 made of a conductive material is etched so that the selectivity with respect to the insulating film 10 is 1. Etch back is performed until it is exposed, and then the photo resist 1 remaining in the stepped portions such as the contact portion 1 with the diffusion layer 3 is removed. Finally, as shown in Fig. 1(e) 1ζ, a second layer of aluminum is formed by a sputtering method, the photo resist 1 (not shown) is buttered, and the etch is etched by a dry etching method. A two-layer aluminum wiring 11 is formed.
なお、上記実施例では2層配線の場合について説明した
が、3層以上の配線の場合であってもよく、また、拡散
層3あるいはゲー1−6とのコンタク1・部の配線上に
行っても上記実施例と同様の効果を秦ずる。In the above embodiment, the case of two-layer wiring was explained, but the case of wiring of three or more layers may also be used. However, the same effect as in the above embodiment can be obtained.
以上説明したように、この発明は、第1層のアル{配綿
をパター″:;ノゲしt:後、その」二ζζアノl−ε
以外の導電性材料からなる膜を所要の大きさにバターニ
ングした後、全面CこMrR絶縁膜を形成し、その後レ
ンス1・バターノをマスクにして導電性材料からなる膜
の表面が露出ずるまで層間絶縁膜のエッチングを行い、
その後、導電性材料からなる膜に接触せしめて第2暦の
アルミ配線を形成し、これらの工程により多層構造のア
ルξ配線を形成するので、マスク合わせ工数を増やさず
に第1層,第2層のアルミ配線間のオ−ミック性の良好
な半導体装置が得られる効果がある。As explained above, the present invention is based on the first layer of cotton.
After buttering a film made of a conductive material other than the above to the required size, a CMR insulating film is formed on the entire surface, and then using Lens 1/Batano as a mask, it is patterned until the surface of the film made of a conductive material is exposed. Etching the interlayer insulation film,
After that, a second aluminum wiring is formed in contact with a film made of a conductive material, and these steps form a multilayered aluminum wiring, so the first and second layers can be connected without increasing the number of mask alignment steps. This has the effect of providing a semiconductor device with good ohmic properties between the aluminum wiring layers.
第1図は乙の発明の一実施例による半導体装置の製造方
法を示す工程断面図、第2図は従来の半導体装置の製造
方法を示す工8断面図である。
(5)
(6)
図において、1は半導体基板、2はウエ)b,3は拡散
層、4はフィールド酸化膜、5はゲーl・酸化膜、6{
よゲ−1・、7はスムースコ−1・、8ば第1層のアル
ミ配線、9は導電性材料からなる膜、10は層間絶縁膜
、11は第2層のアルミ配線である。
なお、各図中の同一符号は同一または相当部分を示す。FIG. 1 is a process cross-sectional view showing a method for manufacturing a semiconductor device according to an embodiment of the invention, and FIG. 2 is a process cross-sectional view showing a conventional method for manufacturing a semiconductor device. (5) (6) In the figure, 1 is the semiconductor substrate, 2 is the wafer, 3 is the diffusion layer, 4 is the field oxide film, 5 is the gate l/oxide film, 6
Reference numeral 1., 7 indicates a smooth coat 1., 8 indicates a first layer of aluminum wiring, 9 indicates a film made of a conductive material, 10 indicates an interlayer insulating film, and 11 indicates a second layer of aluminum interconnection. Note that the same reference numerals in each figure indicate the same or corresponding parts.
Claims (1)
装置の製造方法において、第1層のアルミ配線をパター
ニングした後、その上にアルミ以外の導電性材料からな
る膜を所要の大きさにパターニングした後、全面に層間
絶縁膜を形成し、その後レジストパターンをマスクにし
て前記導電性材料からなる膜の表面が露出するまで前記
層間絶縁膜のエッチングを行い、その後、前記導電性材
料からなる膜に接触せしめて第2層のアルミ配線を形成
し、これらの工程により多層構造のアルミ配線を形成す
ることを特徴とする半導体装置の製造方法。In a method for manufacturing a semiconductor device in which two or more layers of aluminum wiring are formed on a semiconductor substrate, after patterning the first layer of aluminum wiring, a film made of a conductive material other than aluminum is patterned on top of it to the required size. After that, an interlayer insulating film is formed on the entire surface, and then the interlayer insulating film is etched using the resist pattern as a mask until the surface of the film made of the conductive material is exposed. 1. A method of manufacturing a semiconductor device, comprising forming a second layer of aluminum wiring in contact with the aluminum wiring, and forming a multilayer aluminum wiring through these steps.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15897289A JPH0322537A (en) | 1989-06-20 | 1989-06-20 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15897289A JPH0322537A (en) | 1989-06-20 | 1989-06-20 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0322537A true JPH0322537A (en) | 1991-01-30 |
Family
ID=15683399
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15897289A Pending JPH0322537A (en) | 1989-06-20 | 1989-06-20 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0322537A (en) |
-
1989
- 1989-06-20 JP JP15897289A patent/JPH0322537A/en active Pending
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