JPH0322539A - Manufacturing method of semiconductor device - Google Patents

Abstract

PURPOSE:To remove a charge on a photoresist through a high-melting point metal film and prevent dielectric breakdown by a method wherein the high- melting point metal film is applied over the whole surface of a substrate when a high-concentration ion-implantation for forming diffused layers is performed. CONSTITUTION:Low-concentration impurity regions 5 are formed and thereafter, sidewalls 6 are respectively formed on the sidewalls of a gate electrode 4. Then, a titanium film 7 which is a high-melting point metal film is applied over the whole surface of a substrate. Then, high-concentration impurity regions 8 are formed by ion-implanting arsenic from over the titanium film 7 using a photoresist 10 as a mask and thereafter, an annealing is performed by an RTA (Rapid Thermal Anneal) method. Thereby, a silicification reaction is caused in the interfaces, where the surface of a polycrystalline silicon film constituting the electrode 4 and the surface of a silicon film constituting the regions 8 come into contact with the titanium film 7, and the titanium film 7 is turned into a titanium silicide (TiSi2) film 9. Then, a field oxide film 2, which is not silicide, and the titanium film 7 on the sidewalls 6 are selectively removed by performing a chemical etching treatment, whereby an LDD type N-channel MOS transistor is obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method for forming a field effect type 1 run disk in a semiconductor device.

[Conventional technology]

Figures 2 (a) to (d) show the conventional 1-lanogistor, especially the L
D D (Lighty Doped Drain
FIG. 3 is a cross-sectional view showing the main steps of forming a )-type transistor. In this figure, 1 is a p-type silicon substrate, 2 is a field oxide film for separating elements, 3 is a gate oxide film, 4 is a gate electrode, 5 is a low concentration impurity region, 6 is a side wall, and 8 is a high concentration impurity region. It is an area.

Hereinafter, a method of manufacturing a conventional LDD type 1 transistor will be explained.

First, as shown in FIG. 2(a), a p-type silicon substrate 1
After forming a field oxide film 2 and a gate oxide film 3 for element isolation, a borin silicon film is deposited on the entire surface, and a gate electrode 4 is formed by photolithography and etching. Next, as shown in FIG. 2(b), after implanting phosphorus ions to form low concentration impurity regions (1) (2) 5, the oxide film is removed by CVD as shown in FIG. 2(c). The sidewall 6 is formed by coating the entire surface using a method and then performing anisotropic etching.

Next, as shown in FIG. 2(d), arsenic ions are implanted to form a high-concentration impurity region 8, thereby obtaining an NMOS+-lanosa transistor having an LDD structure.

[Problem to be solved by the invention]

However, as shown in Fig. 2, in the conventional manufacturing method of the 1-run star, it is necessary to ion-implant arsenic at a high concentration of about 4 x 10 cm -2 to form the source and drain. . In case of second, usually CMOS
When forming a PMOS, the region where the PMOS is to be formed is covered with a PMOS resist 1- (not shown) as a mask for ion implantation. There is a drawback that dielectric breakdown of the gate oxide film 3 occurs due to discharge when the temperature exceeds 100 nm, resulting in a decrease in yield and reliability.

This invention was made to solve the above-mentioned conventional problems, and provides a semiconductor device which prevents dielectric breakdown due to charge-up during ion implantation and further reduces the resistance of the gate 1 and diffusion layer. The purpose is to obtain a manufacturing method for.

[Means to solve the problem]

The method for manufacturing a semiconductor device according to the present invention includes a step of forming a Ga-1 oxide film and a field oxide film for element isolation on a semiconductor substrate, and a step of forming a Ga-1 electrode on the Ga-1 oxide film. , process of implanting low concentration impurity ions into the drain region of the semiconductor unit (sodium plate), forming a low concentration impurity region, process of forming a side wall of an insulator on the side wall of the gate electrode, A process of depositing a melting point metal, a process of injecting a high concentration impurity from above the high melting point metal to form a high concentration impurity region, a process of forming a high melting point metal, a gate electrode, and a semiconductor to form a diffusion layer. The method includes at least a step of siliciding the contacting portion of the substrate, and a step of removing high melting point metal other than the portion where the silicide has been turned into a noid.

[Effect]

In this invention, when (3) (4) high-concentration ion implantation is performed to form a diffusion layer, the high melting point metal is exposed over the entire surface, so that the charges built up in the photoresist 1 are escapes due to the high melting point metal, thereby preventing dielectric breakdown. Also, since the high melting point metal remains as a silicide on the gate electrode and the diffusion layer, the resistance of the gate electrode and the diffusion layer is reduced. be able to.

〔Example〕

An embodiment of the present invention will be described below.

FIGS. 1(.) to 1(f) are process cross-sectional views showing an embodiment of the method for manufacturing a semiconductor device of the present invention.

As shown in Fig. 1 (.) - (C), Fig. 2 (a) - (
After forming a low concentration impurity region 5 in the same manner as in the conventional example shown in C), a side wall 6 is formed on the side wall of the gate I electrode 4. Next, as shown in FIG. 1(d), a high melting point metal such as titanium 7 is deposited over the entire surface. Next, arsenic is ion-implanted from above the titanium 7 using the photo resists 1 and 10 as masks to form a high concentration impurity region 8 as shown in FIG. 1(e).
Annealing is performed using a rapid thermal annealing method. As a result, the polysilicon of the gate electrode 4 and the silicon surface of the high concentration impurity region 8 and the titanium 7
An oxidation reaction occurs at the interface where
), titanium silicide (T I S 12
) becomes 9. Next, a chemical etch nog process is performed to selectively remove unsilicided field oxide film 2 and titanium 7 on sidewalls 6, thereby obtaining an LDD type NMOSI-transistor.

According to the above method, when arsenic is ion-implanted at a high concentration, the charges built up on the photoresist 1, 10 escape through the titanium 7, which is a high melting point metal, and do not cause dielectric breakdown. Further, titanium silicide 9 is formed as a low resistance layer on the gate electrode 4 and the diffusion layer by the silicidation reaction and the selective removal of titanium 7, so that low gate resistance and low diffusion resistance can be obtained.

Although titanium 7 was used as the high melting point metal in the above embodiment, the same effect can be obtained by using other high melting point metals having similar properties.

(5) (6) Furthermore, in the above embodiments, the formation of NMOSI- transistors has been described, but the same effect can be obtained in the formation of PMOS+ transistors.

〔Effect of the invention〕

As described above, the present invention relates to a process of forming a gate 1 oxide film and a field oxide film for element isolation on a semiconductor substrate, a process of forming a gate 1 electrode on a gate oxide layer, and a process of forming a gate 1 electrode on a gate oxide layer. A step of implanting low concentration impurity ions into the source and drain regions of the substrate to form a low concentration impurity region, a step of forming sidewalls of an insulator on the side walls of the gate electrode, a step of depositing a high melting point metal on the entire surface,
A process of implanting high concentration impurity ions from above the high melting point metal to form a high concentration impurity region, a process of siliciding the contact area between the high melting point metal and the semiconductor substrate forming the gate electrode and the diffusion layer, silicide Since it is formed by a step of removing the high melting point metal other than the part that has become oxidized, the charge that has increased in the photo resist 1 due to the high concentration ion implantation can be released through the high melting point metal. Therefore, dielectric breakdown of the gate oxide film can be prevented, and
By forming the oxide compound, it is possible to reduce the resistance of the gate resistance and the diffusion resistance, which has the effect of making it possible to provide a highly reliable semiconductor device with a low defect rate and high performance.

[Brief explanation of drawings]

FIG. 1 shows an LDD type NMOSI according to an embodiment of the present invention.
- Cross-sectional view showing the process of forming a transistor; FIG. 2 is a cross-sectional view showing the process of forming a conventional LDD type NMOSI transistor. In the figure, 1 is a p-type silicon substrate, 2 is a fine oxide film, 3 is a gate oxide film, 4 is a gate electrode, 5 is a low concentration impurity region, 6 is a side wall, 7 is titanium, and 8 is a gate oxide film. 1 is a high concentration impurity region, 9 is titanium silicide, and 10 is a high concentration impurity region. Note that the same reference numerals in each figure indicate the same or corresponding parts.

Claims (1)

[Claims] a step of forming a gate oxide film and a field oxide film for element isolation on a semiconductor substrate; a step of forming a gate electrode on the gate oxide film; a source of the semiconductor substrate;
A step of implanting low concentration impurity ions into the drain region to form a low concentration impurity region, a step of forming sidewalls made of an insulator on the side walls of the gate electrode, a step of depositing a high melting point metal on the entire surface, and a step of depositing the high melting point metal on the entire surface. a step of implanting high concentration impurity ions from above the metal to form a high concentration impurity region, a step of siliciding the contact portion of the high melting point metal and the semiconductor substrate forming the gate electrode and the diffusion layer, and the silicide. 1. A method of manufacturing a semiconductor device, the method comprising at least the step of removing high melting point metal other than the part that has become oxidized.