JPH03225419A - Adder - Google Patents

Abstract

PURPOSE:To decrease the number of constituent elements while holding fastness by using a correcting circuit which can be composed of a small number of elements instead of providing two adding circuits in a block. CONSTITUTION:At every small number of bits in the block which is divided at every the small number of bits, the addition is executed in order to perform entire addition and an adding circuit 1 which is applied with 0 at the least significant bit as a carrier at all times outputs the sum of the respective bits and the carry of the block. Further, when a carry from a precedent-stage block is 1, the correcting circuit 2 in the block decides whether or not the sum of respective bits outputted by the adding circuit 1 is inverted and generates a signal, bit by bit. Inverting circuits 3 and 4 inputs the sum outputted by the adding circuit 1 and the signal generated by the correcting circuit 2, inverts bits which need to be inverted, and outputs the sum of the block. Consequently, the number of elements can be decreased while maintaining the fastness of a conventional selection type adder.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to adders in electronic circuits.

[Prior Art] FIG. 5 is a block diagram of a conventional selective 16-bit adder. In the figure, A(0) to A(15), B
(0) to B(15) are signals indicating each bit of the number to be added, 5 is a pro-link that performs addition every 4 bits,
(0) to 5(15) indicate the sum of each bit output by each block 5, and 7 indicates a carry signal line for sending a carry output from each block 5 to the next block 5. FIG. 6 is a block diagram of the internal circuit of block 5 in FIG. In the figure, 1 is a 4-bit Manchester type adder circuit in which the carry added to the least significant bit is fixed to 0;
0 is 4 with the carry added to the least significant bit fixed at 1.
Bit's Manchester type adder circuit 11 is an adder circuit 1 and an adder circuit l by the carry output from the previous stage block 5.
Selection circuit that selects either O, 6 selects logic gate C
(i-1) is the inverted signal of the carry output from the previous block 5, and C(i+3) is the inverted signal from block 5 or the next block 5.
5o(i) to 5o(i+3) are the carry signals to be output to the adder circuit 1.
) ~5l(i+:l) is the sum signal of each bit output from the adder circuit (lO), and Go(i+3) is the sum signal of each bit output from the adder circuit (lO).
) or the inverted number 13 of the output carry is C:1(i+3
) is the inverted 43 of the carry output from the adder circuit (10).
5(i) to S(i+4) indicate the sum number 43 of the final block 5 selected by the selection circuit II. FIG. 7 is an internal circuit diagram of the adder circuit 1 of FIG. 6. In the figure, 8 is an n-channel complementary metal oxide film transistor, 9 is an n-channel complementary metal oxide film transistor, and V
cc is a power line, Vss is a ground line, C is a clock signal, P(i+1) to P(i+3) are propagation signals to the signal and generated from B, G(i) to G(i+3) are to the signal and The generated signal generated from B, Co(i) ~Co(i
+3) indicates a signal obtained by inverting the carry generated by each bit in the adder circuit 1. Figure 8 shows the adder circuit I in Figure 6.
9 is an internal circuit diagram of the selection circuit 11 of FIG. 6. In each figure, the same symbol indicates the same thing, and i in the symbol indicates i=0 for each block 5. i=4.
i=8, 1=12, and j in the symbol represents each selection circuit 11.
j・0, 1, 2.3 for each.

Next, the operation of the conventional selective adder will be explained. Fifth
As shown in the figure, addition is performed by dividing into blocks 5 each containing 4 bits. Each block 5 receives the carry output from the previous block 5 through the carry signal line 7, generates a sum of each bit and a carry to be output to the next block 5, and performs the total 16-bit addition. The internal operation of each block 5 will be explained with reference to FIG. Signals A(i) to A(i+3) indicating the number of 4 bits to be added
, B (i) to B (i+3) are input to the adder circuit (1) and the adder circuit (10). Here, the operations of the adder circuit (1) and the adder circuit 1D will be explained. First, the adder circuit 1 uses a logic circuit to generate the propagation signal P and the generated signal G in FIG. 7, although they are not shown in the figure.
n), P(n)=8(n)○B(n) (however, n”i −i+3).

When clock i, τ CKh)1, signal Co(i) ~
Go(i÷3) or the appearing node is precharged,
At this time, the signals P(i) ~ P(i+3), G(j)
~G(j+3) The transistor turns on and off. Next, when the clock signal Ck becomes 0, the output signal Go
The note where (i) ~ Co (i + 3) appears is conditionally discharged, and the signal Go (i) ~ C: o (i +:
I) is obtained. Is the circuit configured such that the note on which the signal (:o(i) appears is not discharged unless the signal G(i) is 1? This means that the adder circuit 1 is a carry added to the least significant bit or is always 0. Next, the adder circuit lO, which is a similar circuit as shown in Fig. 8, or the transistor that inputs the signal D(i) is connected to the ground line Vss. As a result, both signals 5P(i) and G(i) become 00 and CI(j) becomes 1. This means that the carry added to the adder circuit 10 or the least significant bit is always 1.

The adder circuit l and the adder circuit IO receive the signal G obtained in this way.
o(i) ~C:o(i+3), (:1(i) ~(:
l(i+3) and the propagation signals P(i) to P(i+3), using a logic circuit (not shown), 5o
(n)=(:o(n)+P(n), 5t(n)=CI
(n) +P (n), the signal 5o(i)
~5o(i+3).

51(i) to 5I(i+:]) (tap n
=l~i+3).

Next, returning to FIG. 6, the signals 5o(i) to 5o(i+3
), 5l(i) to 51(i+3) are each input to the selection circuit 11. As shown in FIG. 9, the selection circuit 11 turns on the transistor 5o(j) when the carry from the previous stage is 0, and turns on the transistor 5l(j) when the carry from the previous stage is 1. The correct signal is selected to generate 5(i) to S (i +3). Signal output from block 5 to the next block 5 (: (i + 3)
is Go(j+3
).

e=>C(i+3)=C(i)−CI(i+3)+
It is generated using the logic Co(i+3).

In this selective adder, the red path through which a carry is transmitted passes through the logic gate 6 in FIG. 6, and each block 5 has two stages of gates. Adder circuit 1 in each block 5 Adder circuit I
Regardless of the speed of carry propagation by O, addition can be performed at high speed by propagating all carries.

In this adder, a Manchester type adder circuit using a dynamic circuit is used as the adder circuit in the block 5, or there is no particular need to use this adder circuit.

[Problem to be solved by the invention] Since the conventional selective adder was configured as shown below, it is necessary to configure one block to increase the speed.
There was a problem in that the number of elements constituting the adder was increased because two adder circuits were used.

The present invention has been made in order to solve the problems mentioned above, and aims to provide an adder that maintains the high speed of the conventional selective adder and can reduce the number of elements. .

[Means for Solving the Problems] In order to perform addition of multiple bits, an adder according to the present invention includes several divided blocks that perform addition for each small number of bits, and a carrier output from this block. is input to another block, and in an adder that has a carry signal line that connects the blocks in series, addition is performed for each minority bit assigned to the block within the block, and the carry added to the least significant bit is If the adder circuit is always 0 and the carry of the previous block input through the carry signal line into the block is 1, determine whether to invert the sum of each bit output by the adder circuit, and The block is equipped with a correction circuit that generates a signal, and an inverting circuit within the block that inverts the sum of bits that need to be inverted among the sums of each bit output from the adder circuit using the signal generated by the correction circuit.

[Operation] In order to perform overall addition, the adder in the present invention performs addition for each fractional bit in a block divided into fractional bits, and adds a carry that is always added to the least significant bit or an addition that is always 0. The circuit outputs the sum of the valley bits and the carry of that block. If the carry from the previous block is 1, the correction circuit within the block determines whether or not to invert the sum of each bit output from the adder circuit, and generates a signal for this purpose for each bit.

The inversion circuit uses the sum output from the adder circuit and the tl of the correction circuit,
Input the sign, invert the same node that needs to be inverted, and output the sum as a block. Further, the carry output to the next stage block is generated from the carry output from the adder circuit, the carry input from the previous stage block, and the signal generated by the correction circuit via a logic gate.

In this way, the sum of each bit of each block is summed up by 1, and the carry output from each block is input to the next block via the carry signal line, and the total sum is added.

[', (Embodiment) Hereinafter, an embodiment of the invention will be described with reference to the drawings.The block diagram of an adder according to an embodiment of the invention is shown in FIG. 5, which is the same as the conventional adder. FIG. 1 is a block diagram of the internal circuit of block 5 in FIG. A correction circuit 3 determines whether to invert or not and generates a signal for that purpose, and 3 inverts the sum of the bits that need to be inverted out of the sum of each bit output from the adder circuit 1 using No. 13 generated by the correction circuit 2. An inverting circuit 4 has the same function as the inverting circuit 3 but has an opposite logic to the input signal; 12 is a logic gate; I(i) to I(i+3) indicate signals generated by the correction circuits; 3 is an internal circuit diagram of the correction circuit 2, and FIG. 3 is an internal circuit diagram of the inversion circuit 3 in FIG.

In the figure, j takes i=1.2.3. Figure 4 is the first
It is an internal circuit diagram of the inverting circuit 4 in the figure. In addition, in the drawings, the same symbols as those of the conventional device are the same or equivalent parts.

Next, the operation of this embodiment will be explained. Note that this embodiment is also the same as the conventional one (16-bit adder,
As shown in the block diagram of FIG. 5, the total addition is performed by dividing into blocks 5 each containing 4 bits. The internal operation of each block 5 will be explained next. Signals A(i) to A(i+3), B(i) to B(i+3) indicating the number of 4 bits to be added
is input to the addition circuit l and the correction circuit 2. The adder circuit 1 is the same as the conventional one, and assuming that the carry added to the least significant bit is 0, the adder circuit 1 receives signals 5o(i) to 5o(i
+3), (d(i+3)).When the carry input from the previous block 5 is 1, the correction circuit 2 outputs the signals 5o(i) to 5o(i+3) output from the adder circuit 1.
It detects which bits in the table should be inverted to produce the correct result. For example, the number to be added is 10 in binary
Assuming 01 and 00IO, the result of addition when the carry added to the least significant bit is 0 is 1011.

Here, if a carry is added to the least significant bit, it becomes 1100, so it is sufficient to invert the first and second bits from the least significant bit of 1011. It is necessary to add 1 to the least significant bit of the bit to be inverted to determine to which bit the carry generated by this is propagated, and this is determined by the propagation signal P(i) generated in the adder circuit ~P(
i÷3) is given as the information. The operation of the correction circuit 2 will be explained with reference to FIG. If the propagation signal is 1, the n-channel transistor to which it is input is turned on, the P-channel transistor is turned off, and the signal - becomes 0, indicating that a carry is propagated. If the propagation signal is 0, the n-channel transistor to which it is input is turned off, the P-channel transistor is turned on, and the signal I becomes 1. The bits higher than the bit where the propagation signal becomes O are all 1 regardless of whether the propagation signal is 0.1. In this way, the generated signals I(i) to I(i+3) and the previous block 5
A signal C(i-1), which is the inverted carry input from block 5, is input to the logic gate 12 as shown in FIG.
(i+3) is input to the inversion circuit 39 and the inversion circuit 4.

The inverting circuit 3 is constructed as shown in FIG. 3, and is configured to invert SoU according to an input signal. The inverting circuit 4 is constructed as shown in FIG. 4, and has a logic opposite to that of the inverting circuit 4 with respect to the input. The sums 5(i) to S(
i+3) is output. Also, the signals Go(i+4), C(
i-1) and I(i+3), an inverted carry signal is generated which is output to the next stage block 5 via the logic gate 6.

The adder of this embodiment is the same as the conventional selective adder, and the path through which carry is transmitted is two stages of logic gates per block 5, and the speed is the same. Then, instead of providing two adder circuits in the block 5, it can be configured with a smaller number of elements.

By using a modified circuit, the same performance as a conventional adder can be achieved with a circuit smaller in size than a conventional adder.

It should be noted that although the above embodiment shows the case where a Manchester type adder circuit using a dynamic circuit is used, there is no need to specifically limit it to this.

[Effects of the Invention] As described above, according to the present invention, it is possible to reduce the number of constituent elements while maintaining the high speed of the conventional selective adder, and it is possible to realize an extremely inexpensive and high-performance adder. There is.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an internal circuit of a block 5 that performs addition for each minority bit of an adder, which is an embodiment of the present invention, and FIG. 2 is a modification circuit 2 of the adder, which is an embodiment of the present invention.
3 is an internal circuit diagram of an inverting circuit of an adder, which is an embodiment of the present invention. FIG. The internal circuit diagram of the circuit, FIG. 5 is a block diagram of an adder common to the conventional example and the present invention, FIG. 6 is a block diagram of the internal circuit of the divided block 5 of the conventional example, and FIG. 7 is the conventional example and the present invention. An internal circuit diagram of a Manchester-type adder circuit in which the carry to the common least significant bit is fixed to 0. FIG. 8 is an internal circuit diagram of a conventional Manchester-type adder circuit in which the carry to the least significant bit is fixed to 1. The figure shows an internal circuit diagram of a conventional selection circuit. In the figure, 5 is several blocks that perform addition for each fractional bit, 7 is a carry signal line, 1 is an addition circuit that fixes the carrier to the least significant bit at 0, 2 is a correction circuit, 3 and 4 are inversion circuits. shows. Note that the symbols in the figures refer to the same or equivalent parts.

Claims (1)

[Claims] In order to perform addition of multiple bits, there are several divided blocks in which addition is performed for each small number of bits, and a carry outputted from this block is input to the other blocks, and between the blocks. an adder having a carry signal line connecting in series, an adder circuit that performs addition for each minority bit assigned to the block within the block, and a carry added to the least significant bit is always 0; A modification that determines whether to invert the sum of each bit output from the adder circuit and generates a signal for inverting it when the carry of the previous block inputted through the carry signal line into the block is 1. an adder comprising: a circuit; and an inversion circuit in the block that inverts the sum of the bits that need to be inverted among the sums of the bits output by the adder circuit according to a signal generated by the correction circuit. .