JPH03225454A - Integrated circuit for cache memory control - Google Patents

Abstract

PURPOSE:To use the burst bus cycle of a microprocessor by informing the microprocessor that burst access is allowed through a burst permission output terminal and outputting data from a cache memory continuously with a strobe signal from a signal generating circuit at the same time. CONSTITUTION:When the microprocessor 101 executes the burst bus cycle, a 1st address is outputted between 1st two clocks and an increased address is outputted, clock by clock, from a next clock. A corresponding strobe signal becomes active timing with the output period so that data are outputted from a corresponding data bank in a data memory bank 103. A common high-order address is inputted to the data memory bank 103, so the strobe signal is inputted while an address is already determined. Consequently, the burst bus cycle of the microprocessor 101 can easily be used.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an integrated circuit for controlling a cache memory connected to a microprocessor, and particularly to an integrated circuit for controlling a cache memory that receives burst access requests from the microprocessor. .

[Conventional technology]

As the performance of microprocessors has improved, microprocessors that support not only single bus cycles but also burst bus cycles have appeared. Hereinafter, the microprocessor will be referred to as MPU.

In single bus cycle, in one bus cycle,
Although one word of data is fetched, MPUs that support burst bus cycles typically fetch four consecutive words of data in one bus cycle. In terms of timing, a single bus cycle requires two clocks per bus cycle. In contrast, in a burst bus cycle, it takes two clocks to fetch the first word and one clock per word to fetch the remaining three words, totaling five clocks.

This burst bus cycle is mainly used when exchanging data in the cache memory built into the MPU.

Generally, a cache memory consists of a plurality of blocks, and the entire cache memory is managed using each block as a unit. In the MPU's built-in cache memory, each block is divided into four sub-blocks, and when replacing data, the data is not replaced in the entire block, but only in one sub-block that contains the necessary data. Replace the data.

On the other hand, if you use a burst bus cycle,
- Sometimes the data of all subblocks within the same block are swapped. Therefore, it is possible to significantly shorten the time required to replace subblock data. Furthermore, this greatly improves the hit rate of the built-in cache memory, resulting in an improvement in the overall performance of the MPU.

From the above, it follows that in an MPU that can use burst bus cycles, it is better to use burst bus cycles as much as possible.

When using such burst bus cycles, the nibble mode is generally used since the normal mode of dynamic memory requires too long an access time.

On the other hand, in the case of a system in which a cache memory is connected to the outside of the MPU, it is extremely difficult to perform burst access to the external cache memory. The reason for this is that external cache memories are generally designed to support a single bus cycle of two clocks, so data cannot be fetched using the (1) clock. Furthermore, since the data memory used as the external cache memory is a static memory, the nibble mode cannot be used.

For the above reasons, when using an external cache memory, single bus cycles must be used instead of burst bus cycles.

On the other hand, the cache memory built into the MPU has a small cache capacity due to its nature, and in order to fully utilize the performance of the MPU, it is necessary to connect an external cache memory with a larger capacity.

[Problem to be solved by the invention]

A cache memory connected to the outside of the MPU requires two clocks even when accessed at the highest speed. Furthermore, since the data memory used as the external cache memory is a static memory, the nibble mode cannot be used.

Due to these circumstances, burst bus cycles cannot be used when a cache memory is connected to an MPU that supports burst bus cycles. Therefore, this cache memory has the disadvantage that it cannot fully utilize the performance of an MPU that supports burst bus cycles.

[Differences between the invention and the prior art]

The present invention relates to a cache memory control device that supports burst bus cycles and is connected to a microprocessor.The present invention enables the use of burst bus cycles of the microprocessor, which was previously impossible, and improves the performance of the entire system. Has a point.

[Means to solve the problem]

In a cache memory control integrated circuit connected to a microprocessor, burst request input terminal means for accepting a burst access request from the microprocessor, burst permission output terminal means for outputting burst permission to the microprocessor, burst - A signal generation circuit that generates an access strobe signal; a burst access request is received from the microprocessor via the burst request input terminal, and the requested data is sent to the cache controlled by the cache memory control integrated circuit; If the burst access exists in the memory, permission for the burst access is transmitted to the microprocessor via the burst permission output terminal, and at the same time, a strobe signal from the signal generation circuit causes the microprocessor to continuously access the memory from the cache memory. It is characterized by outputting data.

〔Example〕

The configuration and operation of the present invention will be explained in detail below with reference to the drawings.

[Example 1] Figure 1 shows the system configuration on the Honjitsuo side.

In FIG. 1, the microprocessor 101 is a microprocessor equipped with a terminal for outputting a burst request signal, the data memory bank 103 is a memory that holds cache data, and the cache memory control device 102 is a microprocessor equipped with a terminal that outputs a burst request signal. This is a control device that inputs a burst request, outputs a burst permission signal, and outputs a strobe signal to the data memory bank 103.

Data memory bank 103 consists of four memory banks, each of which receives the same address from microprocessor 101. Cache memory control device 102
outputs a strobe signal to each of the four memory banks in data memory bank 103, and data is output from the corresponding memory bank to the data bus.

Continuous data is stored in a corresponding data area of each memory bank. That is, the first memory bank contains a data whose lower two bits are OO, and 4
The second memory bank stores data with the lower two bits of the address being 11.

FIG. 2 shows the cache memory control circuit 1 in FIG.
Part of 02 is shown.

In FIG. 2, the input terminal 201 is a terminal for inputting a burst request signal from the microprocessor, the output terminal 202 is a terminal 1 for outputting a burst permission signal to the microprocessor, and the AND gate 203 is a terminal for inputting a burst request signal from the input terminal 201. An AND gate that ANDs the burst request signal and the hit signal of the cache memory. - Timing generator 204 is a timing generator that creates the timing of the strobe signal for the data memory bank. - Latch 205 is supplied from the microprocessor 101. The decoder 206 is a decoder that decodes the address held in the latch 205.

When the cache memory hits in response to a data fetch from microprocessor 101, a hit signal is asserted. If there is a burst request signal from the microprocessor 101 at this time, this request signal and the hit signal are ANDed, and the output is sent to the microprocessor 101 from the output terminal 202 as a burst permission signal.
will be notified.

The timing generator 202, when the burst enable signal is asserted and the bus cycle signal is input,
Instructs latch 205 to hold the address from microprocessor 101. Since the address from the microprocessor 101 increases at predetermined intervals, the timing generator 202 outputs a signal so that the latch 205 latches the address in accordance with the timing.

Decoder 206 decodes the address held in latch 205 and activates the corresponding one of the four strobe signals. When the value of latch 205 is 00, strobe signal 1 becomes active, and when the value of latch 205 is 11, strobe signal 4 becomes active. Actually S)o-
Timing generator 202 directs the timing of activating the activation signal.

When the microprocessor 101 executes a burst bus cycle, it outputs the first address during the first two clocks, and outputs an address incremented every clock from the next clock.

Since the microprocessor 101 outputs four addresses in total, the respective output periods are 2 clocks, 1 clock, 1 clock, and 1 clock.

In accordance with this output period, data memory bank 10
The corresponding strobe signal becomes active so that data is output from the corresponding data bank in No. 3.

Since a common upper address is input to the data memory bank 103, the strobe signal is input with the address already determined. This results in
It is possible to access data at high speed.

Through the above operations, when the cache memory is hit and there is a burst request from the microprocessor 101, a strobe signal for controlling the data memory bank 103 is generated. During the burst period, four strobe signals are activated in sequence according to requests from microprocessor 101. If the cache memory is not hit, the burst request is not allowed.

[Example 2] In Example 1, the number of times the strobe signal is output during the burst period is fixed at four times, but in this example, it can be arbitrarily selected from four times or less. It has the characteristics of

This allows you to adjust the burst data to suit your system configuration.
The number of fetches can be arbitrarily selected.

FIG. 3 shows the system configuration in this embodiment.

In FIG. 3: - Register 307 is a register that holds the number of data fetches during a burst.

The basic operation is the same as in the first embodiment. register 30
7, the timing generator 30
4 sends a signal to the latch 305 and decoder 306 as many times as necessary. If the value of register 307 is 2,
The latch 305 holds the address twice, and the decoder outputs the strobe signal twice. In this case, the first address is output for two clocks, and the next address is output for one clock.

〔Effect of the invention〕

As explained above, when connecting a cache memory externally to a microprocessor that supports burst bus cycles, burst bus cycles cannot be used; By using the circuit shown in the present invention, it becomes possible to easily use burst bus cycles, increasing the hit rate of the cache memory built into the microprocessor, and improving the performance of the entire system. becomes.

Additionally, since four sets of data memory banks are used, even if static memory with long access times is used,
It is possible to use a burst bus cycle. Furthermore, since the number of data fetches can be arbitrarily selected during the burst bus cycle, it is possible to use the burst bus cycle in accordance with the system bus structure.

[Brief explanation of drawings]

FIG. 1 is a drawing showing the overall configuration of an embodiment. 101...Microprocessor, 102...
...Cache memory control device, 103...
Data Memory Bank FIG. 2 is a diagram showing the configuration of the first embodiment. 201...Input terminal, 202...Output terminal, 203...AND gate, 204...
...timing generator, 205...latch,
206...Decoder FIG. 3 is a diagram showing the configuration of the second embodiment. 307...Register.

Claims (1)

[Claims] A cache memory control integrated circuit connected to a microprocessor, comprising: burst request input terminal means for accepting a burst access request from the microprocessor; burst permission output terminal means for outputting burst permission to the microprocessor; - a signal generation circuit that generates an access strobe signal, wherein there is a burst access request from the microprocessor via the burst request input terminal, and the requested data is sent to the cache controlled by the cache memory control integrated circuit. if present in memory, granting said burst access to said microprocessor;
An integrated circuit for controlling a cache memory, characterized in that data is continuously output from the cache memory in response to a strobe signal transmitted through the burst permission output terminal and simultaneously from the signal generation circuit.