JPH03225470A - Logic circuit restoring method - Google Patents

Abstract

PURPOSE:To shorten a time to restore a circuit diagram by deciding the arrangement of each logic gate by considering by considering both input side distance and output side distance. CONSTITUTION:The arrangement of the logic gate is decided by setting the logic gate whose input side distance is minimum (for example, 1) that is the logic gate whose number is comparatively large as a reference logic gate first. However, when the arrangement is decided, it is corrected by moving the X- coordinate of the reference logic gate considering the output side distance. Thereby, by surely performing the correction of the arrangement of the reference logic gate at an initial stage, the circuit diagram easy to observe can be obtained even without performing re-arrangement and re-wiring processing when another logic gate is arranged at a following stage. In such a way, it is possible to quickly restore a logic circuit as the circuit diagram easy to observe with a simple procedure without requiring the re-arrangement and re-wiring processing of the logic gate by deciding the arrangement considering both the input side distance and output side distance of each logic gate.

Description

[Detailed Description of the Invention] [Summary] This invention relates to a logic circuit restoration method for restoring a logic circuit from logic connection information between a plurality of logic gates, without requiring rearrangement and rewiring of logic gates. A step of determining the input side distance from the input side and the output side distance from the output side of each of the plurality of logic gates, with the aim of quickly restoring the logic circuit as an easy-to-read circuit diagram with a simple procedure. , determine the Y coordinate of the logic gate with the minimum input side distance as the reference logic gate, and determine the Y coordinate of each reference logic gate by the difference between the output side distance of each reference logic gate and the maximum value of the output side distance calculated in advance. A step of arranging each of the reference logic gates by moving the X coordinate of the reference logic gate, and arranging each of the other logic gates in order from the one with the smallest distance on the input side based on each of the arranged reference logic gates. and a step of wiring between all of the arranged logic gates.

[Industrial application field]

The present invention relates to a logic circuit restoration method for restoring a logic circuit from logic connection information between a plurality of logic gates.

More specifically, the present invention can quickly verify errors in a designed mask layout pattern of LSI, etc. to greatly reduce design man-hours, or input an existing mask layout pattern and form it there. In order to examine the logic circuit that is currently in use or to visually understand the circuit written in the circuit description language, the logic circuit is restored as an easy-to-read circuit diagram using a computer, etc. based on the logic connection information extracted from the mask layout pattern. This article refers to a method for restoring logic circuits.

[Conventional technology]

FIGS. 4 and 5 are circuit diagrams for explaining a first example and a second example of a conventional logic circuit restoration method, respectively.

However, here, a method for restoring a circuit diagram using a relatively simple procedure by sequentially arranging a plurality of logic gates along the flow of a signal will be explained as a representative example. Furthermore, in this case, a case will be described in which ten logic gates are arranged according to logic connection information prepared in advance. The above circuit diagram is assumed to be restored along the X coordinate from the input to the output of the plurality of logic gates and the Y coordinate where the terminals of the logic gates are arranged.

In FIG. 4, first, a logic gate whose output side distance from the output side is 1 (a relative value indicating the furthest output side) is placed. Next, a logic gate with an output side distance of 2 is placed. In this case, the Y coordinate is arranged in consideration of the balance with the logic gate whose output side distance is 1. Furthermore, the logic generators after that (output side distance 3.4) are also arranged in order from the one with the smallest output side distance. That is, in the first conventional example, the circuit diagram is restored by determining the arrangement of logic gates starting from the output side where the number of logic gates is small.

On the other hand, in FIG. 5, first, a logic gate whose distance from the input side is 1 (relative value indicating the closest input side) is placed. Next, a logic gate with an input side distance of 2 is placed, and subsequent logic gates are also placed sequentially. That is, in the second conventional example, contrary to the first example (FIG. 4), the circuit diagram is restored by determining the arrangement of logic gates starting from the input side where the number of logic gates is large. .

[Problem to be solved by the invention]

As described above, when restoring a logic circuit as a circuit diagram from logic connection information, conventionally, a plurality of logic gates were arranged one after another along the signal flow from the output side or the input side.

First, in the first conventional example (Fig. 4) in which placement is performed from the output side, the number of logic gates whose placement is initially determined is small (one in the case of Fig. 4), so other logic Gate placement may become difficult. For example, when determining the placement of a logic gate with an output distance of 2, the connection relationship and number of logic gates with an output distance of 3 and 4 are not known, so the logic gate with an output distance of 2 is placed in the Y direction. It is difficult to set a guideline for how far to spread out the space. For this reason, as shown in Figure 4, the balance of the logic gate in the Y direction becomes poor and the circuit diagram becomes difficult to read.
As shown in the flowchart of FIG. 6, it becomes necessary to repeat the process of rearranging and rewiring the logic gates several times until an easy-to-read circuit diagram is obtained.

On the other hand, in the second conventional example (FIG. 5) in which placement is performed from the input side, the number of logic gates for which placement is determined first is large (five in the case of FIG. 5); (4th
The arrangement of the remaining logic gates is easier than in the case shown in Figure). However, in this case, as is clear from FIG. 5, there is a tendency for many logic gates to be placed on the input side.

Therefore, in places where the number of logic gates arranged in the X direction is small (near the center of the Y coordinate), the circuit diagram becomes elongated in the X direction, making it difficult to see. Logic gate rearrangement and rewiring processing must be performed according to the flowchart in FIG. As a result, in both the first and second conventional examples, a problem arises in that it takes time and effort to perform the above-mentioned relocation and rewiring processing. This problem becomes more noticeable as the circuit scale increases and the number of logic gates increases.

The present invention has been made in view of the above-mentioned problems, and provides a logic circuit that can be quickly restored as an easy-to-read circuit diagram using a simple procedure without requiring rearrangement or rewiring of logic gates. The purpose of this invention is to provide a circuit restoration method.

[Means to solve the problem]

FIG. 1 is a flowchart showing the principle of the invention. Here, first, there is a step (step I) of determining the input side distance from the input side and the output side distance from the output side of each of the plurality of logic gates. Next, the Y coordinate of at least one logic gate with the minimum input side distance is determined as a reference logic gate, and the output side distance of each reference logic gate and the maximum of the output side distance calculated in advance are determined. The method includes a step of arranging each of the reference logic gates by moving the X coordinate of each of the reference logic gates by the difference from the value (step 2). Furthermore, based on each of the placed reference logic gates, the other logic gates are sequentially placed from the one with the smallest input side distance (step
). Finally, there is a step (step ①) of wiring between all these logic gates.

[For production]

In FIG. 1, a method that does not require the rearrangement of logic gates is provided by appropriately combining two logic circuit restoration methods that determine the arrangement of logic gates from the output side and the input side.

More specifically, first of all, the input side distance is the minimum (
For example, the arrangement of logic gates 1), ie, the one with a relatively large number of logic gates, is determined as a reference logic gate. However, when determining the arrangement here, the arrangement is corrected by moving the X coordinate of the reference logic gate in consideration of the output side distance. In this way, by reliably correcting the placement of the reference logic gate at the initial stage, an easy-to-read circuit diagram can be obtained without having to perform rearrangement and rewiring processing when arranging other logic gates at a later stage.

Thus, in the present invention, by considering both the input side distance and the output side distance of each logic gate to determine its placement, the process of relocating and rewiring the logic gates is not required and can be performed in a simple procedure. It becomes possible to quickly restore the logic circuit as an easy-to-read circuit diagram.

〔Example〕

FIG. 2 is a flowchart showing one embodiment of the present invention, and FIGS. 3A to 3D are circuit diagrams showing states at each stage of the logic circuit restoration process according to the above embodiment. However, here, a case will be exemplified in which a logic circuit composed of 10 logic gates is restored as a circuit diagram.

In FIG. 2, first, logic connection information indicating connection relationships between logic gates constituting a logic circuit, etc. is stored in advance as a file. Next, the information in this file is read by a computer or the like, and based on this read information, the output side distance from the output side and the input side distance from the input side of each logic gate are determined (step a, Step b). Furthermore, the input side distance is the minimum value, for example 1
The logic gates are set as reference logic gates, and the Y coordinates are determined while the X coordinates of these reference logic gates are matched (step C). FIG. 3A shows the state of the circuit diagram after determining the Y coordinate of the reference logic gate. At this time, the maximum value of the output side distance (shown in parentheses in FIG. 3A) is calculated from among the reference logic gates (step d). In this case, the maximum value of the output side distance is 4. Note that the input side and the output side of the logic circuit can be easily specified by detecting the locations where the input side child of the logic gate is not connected and the location where the output terminal is not connected, respectively. Furthermore, calculate the difference between the output side distance of each reference logic gate whose input side distance is 1 and the maximum value of the output side distance calculated in advance in step d, shift the X coordinate by this difference, and then Place a reference logic gate (step e).

In this case, as shown in Figure 3B, based on the logic gate with an output side distance of 4, the one with an output side distance of 3 is moved to the right (+X direction) by 1, and the output side distance is 2. The object is moved by 2 to the right. After the placement of the reference logic gate is clearly determined in step e, based on the determined reference logic gate, logic gates whose placement has not yet been determined are placed in order starting from those with an input side distance of 2. (Step f). More specifically, the Y coordinate of the logic gate whose placement has not yet been determined is determined based on the Y coordinate of the reference logic gate that has already been determined, and the X coordinate of all logic gates is determined based on the output side distance. There is. The state after determining the placement of all logic gates is 3C.
As shown in the figure. Finally, by making connections between the terminals of these logic gates, it is possible to restore a circuit diagram as shown in Figure 3D, which is more balanced and easier to see than the conventional Figures 4 and 5. g). By displaying this circuit diagram on a CRT or the like, it is easy to quickly verify errors in the created mask layout pattern or visually confirm the existing layout pattern.

In the embodiment described above, there is no need to perform any extra processing such as rearrangement of logic gates at any intermediate stage, so that the processing time can be significantly shortened.

〔Effect of the invention〕

As explained above, according to the present invention, the placement of each logic gate is determined by considering both the input side distance and the output side distance, so it is not necessary to rearrange and rewire the logic gates. It becomes possible to quickly restore a logic circuit as an easy-to-see circuit diagram using simple steps without any trouble. As a result, the processing time for restoring the circuit diagram is significantly reduced.

[Brief explanation of drawings]

Fig. 1 is a flowchart showing the principle of the present invention, Fig. 2 is a flowchart showing an embodiment of the invention, Fig. 3A is a circuit diagram showing the state after determining the Y coordinate of the reference logic gate, and Fig. 3B is the reference. A circuit diagram showing the state after the X coordinate of the logic gates has been moved. Figure 3C is a circuit diagram showing the state after the placement of all logic gates has been determined. Figure 3D is a circuit diagram showing the state after wiring between all logic gates. Figure 4 is a circuit diagram for explaining the first example of the conventional logic circuit restoration method, Figure 5 is a circuit diagram for explaining the second example of the conventional logic circuit restoration method, and Figure 6 is the circuit diagram for explaining the second example of the conventional logic circuit restoration method. It is a flowchart for explaining the conventional problem.

Claims (1)

[Scope of Claims] 1. Based on the logical connection information between a plurality of logic gates, a logic A logic circuit restoration method for restoring a circuit, comprising: determining an input side distance from an input side of each of the logic gates and an output side distance from an output side of each of the logic gates; and the input side distance is a minimum. The Y coordinate of at least one of the logic gates is determined as a reference logic gate, and each arranging each of the reference logic gates by moving the X coordinate of the reference logic gate; and arranging each of the other logic gates from the one with the smaller input side distance based on each of the arranged reference logic gates. A method for restoring a logic circuit, comprising: a step of sequentially arranging the logic gates; and a step of wiring between all the arranged logic gates.