JPH0322565A - Semiconductor device - Google Patents

Abstract

PURPOSE:To improve a semiconductor device of this design in electrical property and reliability and to make a wiring low in resistance by a method wherein a MOS transistor is provided with metal electrodes formed on polycrystalline silicon layers different from each other in size of an undercut. CONSTITUTION:A polycrystalline silicon 5 doped with phosphorus 4 is formed. Then, a silicon oxide film 9 is selectively formed, and furthermore phosphorus 10 is made to dope, whereby only a part where the silicon oxide film is removed is doped with phosphorus 10. By this setup, a phosphorus highly doped region 11 and a phosphorous low doped region 5 are formed on the same polycrystalline silicon 5. Thereafter, a melting point metal 6 is deposited thereon, and a resist 7 is formed. Lastly, the laminated piece is etched by the use of Freon gas through an RIE method or the like using the resist 7 as a mask. At this point, in the phosphorus doped region 11 high in concentration of phosphorus, polycrystalline silicon is becomes fast in etching rate, so that a metal electrode 12 provided with a large undercut 13 can be formed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a device structure of a semiconductor device, particularly a transistor structure.

[Conventional technology]

FIGS. 2(a) to 2(d3) are cross-sectional views showing the process of forming a conventional MOSI transistor.

In this figure, 1 is a silicon substrate, 2 is a silicon oxide film, 3 is polycrystalline silicon, 4 is phosphorus doped by diffusion, 5 is polycrystalline silicon doped with phosphorus 4,
6 is a high melting point metal, 7 is a resist 1, and 8 is a resist 1.
This is a metal electrode that was selectively etched using 7 as a mask.

Next, the manufacturing method will be explained.

A silicon oxide film 2 and polycrystalline silicon 3 are formed on a silicon substrate 1 [FIG. 2(a)]. Next, phosphorus 4 is doped into the polycrystalline silicon 3 by diffusion to lower the resistance of the polycrystalline silicon 3 so that it can be used as a metal material [FIG. 2(b)]. Next, by depositing a high melting point metal 6 on the phosphorus-doped polycrystalline silicon 5, the interconnect resistance is further reduced. Next, resists 1 and 7 are selectively formed on this high melting point metal 6 [FIG. 2(C)]. Finally, RIE (Reactive ton Etch) using Freon gas using resistor as a mask.
The metal electrode 8 is formed by an etching method such as etching.

[Problem to be solved by the invention]

Since the conventional semiconductor device has the structure described above, the part used as the electrode of the MOS+- transistor is also a part with lower resistance (1) (2) than the wiring part etc. Since both have the same cross-sectional shape, it has been difficult to obtain semiconductor devices with excellent characteristics for each.

This invention was made to solve the above problems, and by forming a plurality of metal electrodes with different cross-sectional shapes on the same substrate, it is possible to improve the electrical characteristics of the MOS transistor and the M0 8 1-The purpose is to obtain a metal electrode with an optimal cross-sectional shape for a part where reliability of transistors is important, and a part where low resistance is important for wiring.

[Means to solve the problem]

A semiconductor device according to the present invention includes MOS transistors in which polycrystalline silicon under a metal electrode has different undercut amounts.

[Effect]

The metal electrode of the present invention, which has a cross-sectional shape with a small amount of undercut, has a high source/drain breakdown voltage, and does not cause any abnormality in electrical characteristics between the source and drain. It is advantageous. In addition, metal electrodes with a cross-sectional shape with a large amount of undercut have capacitances between Ga1 and drain and between Ga1 and source (Miller capacitance).
This is advantageous for transistors where high speed is important.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

FIGS. 1(a) to (81) are cross-sectional views according to an embodiment of the present invention, showing each process. In FIG.
The same reference numerals as in the figure indicate the same parts, 9 is a silicon oxide film patterned on the polycrystalline silicon 5, and 10 is a polycrystalline silicon 5 doped with phosphorus 4, the concentration of which is selectively changed. 11 is a phosphorus-doped region with a high phosphorus concentration selectively doped with the phosphorus 10, 12 is a metal electrode in which the lower phosphorus-doped region 11 is undercut, and 13 indicates the undercut portion.

Next, the manufacturing method will be explained.

First, as shown in FIGS. 1(a) and 1(b), polycrystalline silicon (Li(
3) (4) A phosphorus-doped region with a low phosphorus concentration is formed.

Next, by selectively forming a silicon oxide film 9 and doping it with phosphorus 10, phosphorus 10 is doped only in the portion where the silicon oxide film 9 has been removed. In this way, a heavily doped phosphorus region 11 and a lightly doped phosphorus region 5 are formed on the same polycrystalline silicon 5 [Fig.
)). Thereafter, the high melting point metal 6 is deposited in the same manner as in the conventional technique to form the resists 1 and 7 [Fig. 1(d)]
). Finally, by RIE using Freon gas,
Etching is performed using resists 1 and 7 as masks. At this time, in the phosphorus-doped region 11 with a high phosphorus concentration, the etching ray 1 of polycrystalline silicon becomes faster, so that the metal electrode 12 with many undercut portions 13 can be formed. Conversely, in the phosphorus-doped region 5 with a low phosphorus concentration, the etching ray 1 of polycrystalline silicon becomes slower, so that a metal electrode 8 with less undercut is formed.

〔Effect of the invention〕

As explained above, the present invention provides MOSIs with different undercut amounts of polycrystalline silicon underlying metal electrodes.
-Since it has a transistor, metal electrodes with less undercut 1- also have source/drain withstand voltage, and V TH due to offset 1 with the source/drain.
, β can be used for highly reliable l transistors with little variation. Moreover, those with a large amount of undercut have a small Ga1/Miller capacitance, are excellent in high-speed operation, and can be used in transistors that require high-speed performance.

[Brief explanation of drawings]

FIG. 1 is a sectional view showing the manufacturing process of a semiconductor device according to an embodiment of the present invention, and FIG. 2 is a sectional view showing the manufacturing process of a conventional semiconductor device. In the figure, 1 is a silicon substrate, 2 is a silicon oxide film,
3 is polycrystalline silicon, 4 is phosphorus, 5 is phosphorus-doped polycrystalline silicon, 6 is a high melting point metal, 7 is resist 1., 8
1 is a metal electrode, 9 is a silicon oxide film, 10 is phosphorus, 11 is a phosphorus-doped region with a high phosphorus concentration, and 12 is a metal region 113 with many undercuts. (5) (6) The same reference numerals in each figure indicate the same or corresponding parts.

Claims (1)

[Claims] In a MOS transistor having a plurality of metal electrodes having a two-layer structure made of a high melting point metal and polycrystalline silicon on a semiconductor substrate, the MOS transistors have different undercut amounts of polycrystalline silicon in the lower layer of the metal electrode. Characteristic semiconductor devices.