JPH03225823A - Compound semiconductor device - Google Patents

Compound semiconductor device

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Publication number
JPH03225823A
JPH03225823A JP2006190A JP2006190A JPH03225823A JP H03225823 A JPH03225823 A JP H03225823A JP 2006190 A JP2006190 A JP 2006190A JP 2006190 A JP2006190 A JP 2006190A JP H03225823 A JPH03225823 A JP H03225823A
Authority
JP
Japan
Prior art keywords
electrode
layer
film
gaas
metal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2006190A
Other languages
Japanese (ja)
Inventor
Masaya Murayama
村山 雅也
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP2006190A priority Critical patent/JPH03225823A/en
Publication of JPH03225823A publication Critical patent/JPH03225823A/en
Pending legal-status Critical Current

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  • Electrodes Of Semiconductors (AREA)
  • Junction Field-Effect Transistors (AREA)

Abstract

PURPOSE:To make it possible to manufacture an electrode provided with a desired electric characteristic at a good yield by configuring the electrode so that it includes a first metallic film being in contact with a semiconductor substrate and a second metallic film formed through laminating it on a part of the top face of the first metal lic film. CONSTITUTION:An SiO2 film 11 is provided on the surface of an n-type active region 101 being on the top face side of a GaAs substrate 100, and in the opening part 11a thereof, an electrode is formed by configuring it in the following manner. That is, the electrode is made to comprise an AuGe layer 13 a first metallic layer which is formed, being close to the periphery of the opening part 11a, on the n-type active region 101 exposed in the opening part 11a the SiO2 film, and a small areal Pt layer 14 of a second metallic layer which is formed on the AuGe layer 13, being apart from the periphery thereof. Therefore, since no metallic layer being from the second layer on is contacted with the surface of GaAs, the electric characteristic of the field- effect transistor of gallium arsenide is determined only by the first metallic layer 13 being in contact with the surface of GaAs, and the faultiness of the characteristic caused by contacting the semiconductor with the two or more kinds of metals 13, 14 in the one electrode is prevented. Thereby, no deterioration of the characteristic is caused and the yield at which the electrode is manufactured is improved.

Description

【発明の詳細な説明】 〔発明の目的〕 (産業上の利用分野) 本発明は化合物半導体装置の電極に係り、特に化合物半
導体装置のオーミック電極やショットキー電極に好適な
電極の構造を提供するものである。
[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention relates to an electrode for a compound semiconductor device, and particularly provides an electrode structure suitable for an ohmic electrode or a Schottky electrode in a compound semiconductor device. It is something.

(#:来の技術) 化合物半導体装置、特に砒化ガリウム電界効果トランジ
スタ(以下、 GaAsFETと略す)における電極の
構造は一般的に複数の金属からなる多層構造を用いるこ
とが多い。例えばGaAsFETのオーミック電極とし
てはGaAs上にAuGe、次いでptの順で金属膜を
堆積し、その後に熱処理を施してGaAsとAuGeを
合金化してオーミック特性を得るのが一般的である。こ
こでAuGeの上にptを積層する理由は、熱処理によ
って電極表面のモホロジーが悪化するのを防止するため
である。
(#: Current Technology) The structure of an electrode in a compound semiconductor device, particularly a gallium arsenide field effect transistor (hereinafter abbreviated as GaAsFET), generally often uses a multilayer structure made of a plurality of metals. For example, as an ohmic electrode for a GaAsFET, it is common to deposit a metal film on GaAs in the order of AuGe and then PT, and then perform heat treatment to alloy GaAs and AuGe to obtain ohmic characteristics. The reason for laminating PT on AuGe here is to prevent the morphology of the electrode surface from deteriorating due to heat treatment.

また、 GaAsFETのショットキー電極も、 Au
/Tiなどの多層構造にすることが多い。この場合多層
にする理由は、n型GaAsと安定なショットキー接合
を形成する金属としてTiを使用し、電極の電気抵抗を
下げるためにTiよりも抵抗率の低いAuを積層すると
いうものである。
In addition, the Schottky electrode of GaAsFET is also made of Au.
/Ti is often used in a multilayer structure. In this case, the reason for using multiple layers is that Ti is used as the metal to form a stable Schottky junction with n-type GaAs, and Au, which has a lower resistivity than Ti, is layered to lower the electrical resistance of the electrode. .

ここでGaAsFETにおけるオーミック電極の構造を
第3図に断面図で示し、さらにその形成方法を工程順に
断面図で示す第4図(a)、 (b)を参照して説明す
る。まず1例えばイオン注入法により表面にn型能動領
域lotを形成したGaAs基板100上に5in2膜
102、フォトレジスト103の順に設置した後、フォ
トリソグラフィ技術を用いて電極形成予定領域に開口部
102aを形成してn型能動領域101を露出させる。
The structure of an ohmic electrode in a GaAsFET is shown in a cross-sectional view in FIG. 3, and the method for forming the same will be explained with reference to FIGS. 4(a) and 4(b), which show cross-sectional views in the order of steps. First, a 5in2 film 102 and a photoresist 103 are placed in this order on a GaAs substrate 100 on which a lot of n-type active regions are formed on the surface by, for example, ion implantation, and then an opening 102a is formed in an area where an electrode is to be formed using photolithography. to expose the n-type active region 101.

この時、後のリフトオフを行いやすくするために、Si
O□膜102をオーバーエッチすることによりSiO□
膜の開口部をフォトレジストの開口部よりも広くして、
オーバーハング状の構造にする(第4図(a))。次に
AuGe層10層上04層105の順で蒸着を行う(第
4図(b))。その後にリフトオフを行い、次いで熱処
理を施してAuGe層10層上04As基板を合金化さ
せて、オーミック電極を形成する(第3図)。
At this time, in order to facilitate the subsequent lift-off,
By over-etching the O□ film 102, SiO□
The opening in the membrane is made wider than the opening in the photoresist;
Create an overhang-like structure (Figure 4(a)). Next, evaporation is performed in the order of 10 AuGe layers and 04 layers 105 (FIG. 4(b)). Thereafter, lift-off is performed, and then heat treatment is performed to alloy the 04As substrate on the 10 AuGe layers to form an ohmic electrode (FIG. 3).

(発明が解決しようとする課題) 斜上の形成方法では、第1層のAuGe層10層上04
層のpt層105は第4図(b)のように正確に重なっ
て形成されるのが理想的であるが、実際には第2層のp
t層115が第1層のAuGe層10層上04に回り込
んでGaAs基板100上のn型能動領域101に接す
ることが多い(第5図)。ここで問題となるのは金属−
化合物半導体接合の電気的特性は使用する金属の種類に
よって変わることである。具体的には、AuGe−n型
GaAsは熱処理によってオーミック特性を示すように
なるが、Pt−n型GaAsは熱処理前後ともショット
キー特性を示す。従って1本来オーミック接合となるべ
き電極の一部がショットキー接合となり、ptと接して
いる部分のn型GaAsに於ける電子が空乏化するため
、実効的に電流の流れるチャネルがピンチオフされる現
象が起きる。即ち。
(Problem to be Solved by the Invention) In the diagonal formation method, 04
Ideally, the PT layers 105 of the second layer should be formed so as to overlap each other accurately as shown in FIG.
The t-layer 115 often wraps around the top layer 04 of the first AuGe layer 10 and comes into contact with the n-type active region 101 on the GaAs substrate 100 (FIG. 5). The problem here is metal.
The electrical properties of compound semiconductor junctions vary depending on the type of metal used. Specifically, AuGe-n type GaAs exhibits ohmic characteristics through heat treatment, while Pt-n type GaAs exhibits Schottky characteristics both before and after heat treatment. Therefore, a part of the electrode that should originally be an ohmic junction becomes a Schottky junction, and electrons in the n-type GaAs in contact with the PT become depleted, effectively pinching off the channel through which current flows. happens. That is.

本来チャネルに流れるはずの電流値よりも小さい電流し
か得られないだけでなく、バイアスの極性によってチャ
ネルを流れる電流の値が異なるなど、オーミック電極と
しては好ましくない電気的特性を示す(第6図)。この
ような電極を具備したGaAsFETは、所望の高周波
特性が得られなくなると共に、電流の値が著しくばらつ
き、しかも製造歩留りが著しく低下するという欠点があ
った。
Not only can only a smaller current be obtained than the current value that should originally flow through the channel, but the value of the current flowing through the channel varies depending on the polarity of the bias, showing electrical characteristics that are undesirable for an ohmic electrode (Figure 6). . GaAsFETs equipped with such electrodes have disadvantages in that desired high frequency characteristics cannot be obtained, current values vary significantly, and manufacturing yields are significantly reduced.

また同様に多層構造のショットキー電極に於いても、金
属の種類によってショットキーバリアの高さが違うこと
や、用いる金属によっては安定なショットキー接合を形
成できないなどの理由により、上層金属が半導体基板に
接した場合は所望のショットキー特性が得られないとい
う問題があった。
Similarly, in a Schottky electrode with a multilayer structure, the height of the Schottky barrier varies depending on the type of metal, and depending on the metal used, it may not be possible to form a stable Schottky junction. There was a problem in that the desired Schottky characteristics could not be obtained when it came into contact with the substrate.

本発明は上記問題点を除去する新規な電極構造を提供す
ることを目的とするものである。
An object of the present invention is to provide a novel electrode structure that eliminates the above-mentioned problems.

〔発明の構成〕[Structure of the invention]

(課題を解決するための手段) 本発明に係る化合物半導体装置は、化合物半導体基板の
少なくとも能動領域上に順次積層した金属膜でなる電極
が、前記半導体基板に接する第一金属膜と、該第一金属
膜の一部上面に積層して形成されかつその周縁から離隔
した少なくとも第二金属膜を含み構成されてなることを
特徴とする。
(Means for Solving the Problems) A compound semiconductor device according to the present invention includes an electrode made of a metal film sequentially laminated on at least an active region of a compound semiconductor substrate, a first metal film in contact with the semiconductor substrate, and a first metal film in contact with the semiconductor substrate; It is characterized in that it includes at least a second metal film that is laminated on a portion of the upper surface of one metal film and is spaced apart from the periphery of the second metal film.

これにより、前記第二以降の金属膜が半導体基板に接し
ない構造になっている。
This provides a structure in which the second and subsequent metal films do not contact the semiconductor substrate.

(作 用) このように本発明に係る電極の構造では、第2以降の金
属層がGaAs表面に接することがないのでGaAsF
ETの電気的特性はGaAs表面に接している第1の金
属層のみによって決定され、一つの電極に於いて半導体
と二種類以上の金属とが接触することによる特性不良が
防止できる。
(Function) As described above, in the structure of the electrode according to the present invention, since the second and subsequent metal layers do not come into contact with the GaAs surface, the GaAsF
The electrical characteristics of the ET are determined only by the first metal layer in contact with the GaAs surface, and it is possible to prevent characteristic defects due to contact between the semiconductor and two or more metals at one electrode.

(実施例) 以下、本発明の一実施例に係るGaAsFETの電極構
造を第1図に断面図で示し、さらにその形成方法を工程
順に第2図(a)〜(c)に断面図で示す。
(Example) The electrode structure of a GaAsFET according to an example of the present invention is shown in a cross-sectional view in FIG. 1, and the method for forming the same is shown in cross-sectional views in FIGS. .

−例のGaAsFETにおける電極の構造は第1図に示
されるように、GaAs基板100の上面側のn型能動
領域101表面に5in2膜11が設けられており、そ
の開口部11a内に電極が次の構造に形成されている。
- As shown in FIG. 1, the structure of the electrode in the example GaAsFET is that a 5in2 film 11 is provided on the surface of the n-type active region 101 on the upper surface side of the GaAs substrate 100, and the electrode is placed in the opening 11a of the 5in2 film 11. It is formed in the structure of

すなわち、 SiO□膜の開口部11a内に露出したn
型能動領域101上に上記開口部11aの周縁に近接し
て第1金属層のAuGe113と、このAuGe層13
層面3上 金属層のpt層14からなっている。
That is, the n exposed in the opening 11a of the SiO□ film
A first metal layer of AuGe 113 is formed on the mold active region 101 close to the periphery of the opening 11a, and this AuGe layer 13
It consists of a PT layer 14 which is a metal layer on the layer surface 3.

次に一実施例のGaAsFETの電極についてその製造
工程を第2図(a)〜(C)を参照して説明する。表面
にn型能動領域101を形成したGaAs基板100を
準備し、この表面に5in2膜11、フォトレジスト層
12の順で形成した後、電極形成予定領域にフォトレジ
スト層により開口部11aを形成し、n型能動領域10
1が露出される。この時、リフトオフを行いやすくする
ために、SiO□膜の開口部11aをフォトレジストの
開口部よりも広くして、オーバーハング状の構造にする
。(第2m(a))。次に半導体基板表面全面に第1の
金属層としてAuGe層13主1300オングストロー
ムの層厚に蒸着する。この時に、蒸着源周辺を自転する
と共に公転する傘型治具、いわゆる自公転型プラネタリ
・ホルダなどの、蒸着金属粒子が基板表面に対して斜め
方向に入射する基板ホルダを用いて、AuGe層13主
13バーハング状のフォトレジスト層12の下部にまで
入り込むようにする。その結果、AuGe層13主13
トレジスト層の開口部よりも−回り大きく形成される。
Next, the manufacturing process for the GaAsFET electrode of one embodiment will be explained with reference to FIGS. 2(a) to 2(C). A GaAs substrate 100 with an n-type active region 101 formed on its surface is prepared, and a 5in2 film 11 and a photoresist layer 12 are formed on this surface in this order, and then an opening 11a is formed in the area where an electrode is to be formed using the photoresist layer. , n-type active region 10
1 is exposed. At this time, in order to facilitate lift-off, the opening 11a of the SiO□ film is made wider than the opening of the photoresist to form an overhang-like structure. (Second m(a)). Next, an AuGe layer 13 is deposited as a first metal layer to a thickness of 1300 angstroms over the entire surface of the semiconductor substrate. At this time, a substrate holder, such as an umbrella-shaped jig that rotates and revolves around the evaporation source, a so-called auto-revolution type planetary holder, in which the evaporated metal particles are incident on the substrate surface in an oblique direction, is used to form the AuGe layer 13. The main 13 is made to penetrate into the bottom of the photoresist layer 12 in the form of a bar hang. As a result, the AuGe layer 13 main 13
It is formed to be larger than the opening in the resist layer.

(第2図(b)) 、次に第2金属層としてpt層14
を300オングストロームの層厚に蒸着する。この時は
平板型の基板ホルダを用いて、蒸着金属が基板に対して
垂直に入射されるようにする。この結果第2金属層のP
t層14はフォトレジスト層の下部に入り込まないので
、Pt層14の表面積はフォトレジスト層の開口部と同
し大きさで第1金属層のAuGe層13主13−回り小
さくなる(第2図(C))。次いでリフトオフ法により
フォトレジスト及び不要金属層を除去した後、熱処理を
施してオーミック電極を得る(第1図)。
(Fig. 2(b)) Next, a PT layer 14 is formed as a second metal layer.
is deposited to a layer thickness of 300 angstroms. At this time, a flat plate type substrate holder is used so that the deposited metal is incident perpendicularly to the substrate. As a result, P of the second metal layer
Since the T layer 14 does not penetrate under the photoresist layer, the surface area of the Pt layer 14 is the same size as the opening in the photoresist layer, and is smaller around the main AuGe layer 13 of the first metal layer (Fig. 2). (C)). Next, the photoresist and unnecessary metal layer are removed by a lift-off method, and then heat treatment is performed to obtain an ohmic electrode (FIG. 1).

本実施例はGaAsFETのオーミック電極を例にとっ
て説明したが、本発明はこれに限定されるものではなく
、金属−半導体接合による電気的特性を利用する電極で
あれば同様に適用することができる。例えば、GaAs
FETに於けるAu/Ti等の複数の金属層からなるシ
ョットキー電極に本発明を適用することも可能であり、
この場合には第1金属であるTiとGaAsとの間で良
好なショットキー特性を示し、多層にすることにより特
性の劣化を招くことはない。
Although this embodiment has been described using an ohmic electrode of a GaAsFET as an example, the present invention is not limited thereto, and can be similarly applied to any electrode that utilizes the electrical characteristics of a metal-semiconductor junction. For example, GaAs
It is also possible to apply the present invention to a Schottky electrode made of multiple metal layers such as Au/Ti in FET,
In this case, good Schottky characteristics are exhibited between Ti and GaAs, which are the first metals, and the use of multiple layers does not cause deterioration of the characteristics.

また、ここでは化合物半導体としてGaAsを例にとっ
て説明したが1本発明は他の化合物半導体でも適用でき
ることは勿論である。
Furthermore, although GaAs has been described as an example of a compound semiconductor, the present invention can of course be applied to other compound semiconductors.

尚1本実施例では二層の金属層で電極を形成しているが
、三層以上の金属を用いる場合には第3金属層以降を第
2金属層と同じ大きさに形成すればよい。
In this embodiment, the electrode is formed of two metal layers, but if three or more metal layers are used, the third and subsequent metal layers may be formed to have the same size as the second metal layer.

〔発明の効果〕〔Effect of the invention〕

以上述べたように本発明によれば、電極を構成する第2
層以降の金属層が半導体基板に接することがないので接
合の電気的特性は半導体基板と接している第1金属層の
みによって決定され、良好なものが得られる。従って所
望の電気的特性を備えた電極を歩留り良く製造すること
が可能となる。
As described above, according to the present invention, the second
Since the subsequent metal layers do not come into contact with the semiconductor substrate, the electrical characteristics of the junction are determined only by the first metal layer that is in contact with the semiconductor substrate, and good results can be obtained. Therefore, it becomes possible to manufacture electrodes with desired electrical characteristics with high yield.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明に係る1実施例のGaAsFETの電極
の構造を示す断面図、第2図(a)〜(c)は本発明の
1実施例のGaAsFETの製造工程を示すいずれも断
面図、第3図は従来例のGaAsFETの電極の構造を
示す断面図、第4図は従来例のGaAsFETの製造工
程を示すいずれも断面図、第5図は多層構造の電極に於
いて上層金属が半導体基板と接した状態を示す断面図、
第6図はGaAsFETのオーミック特性を表す線図で
1図中のAは本発明の電極による良好な特性、Bは従来
構造の電極による不良な特性を夫々示す。 100・・・GaAs基板、101・・・n型能動領域
、11.102−5in□膜、12.103・7オトレ
ジス11a、102a−開口部、13,104−AuG
e層、14.105,115・・・pt層。 ト層、
FIG. 1 is a cross-sectional view showing the electrode structure of a GaAsFET according to an embodiment of the present invention, and FIGS. 2(a) to (c) are cross-sectional views showing the manufacturing process of a GaAsFET according to an embodiment of the present invention. , FIG. 3 is a cross-sectional view showing the structure of the electrode of a conventional GaAsFET, FIG. 4 is a cross-sectional view showing the manufacturing process of a conventional GaAsFET, and FIG. 5 is a cross-sectional view showing the structure of the electrode of a conventional GaAsFET. A cross-sectional view showing a state in contact with a semiconductor substrate,
FIG. 6 is a diagram showing the ohmic characteristics of a GaAsFET. A in FIG. 1 shows good characteristics due to the electrode of the present invention, and B shows poor characteristics due to the electrode of the conventional structure. 100...GaAs substrate, 101...n-type active region, 11.102-5in□ film, 12.103.7 photoresist 11a, 102a-opening, 13,104-AuG
e layer, 14.105, 115...pt layer. layer,

Claims (1)

【特許請求の範囲】[Claims] 化合物半導体基板の少なくとも能動領域上に順次積層し
た金属膜でなる電極が、前記半導体基板に接する第一金
属膜と、該第一金属膜の一部上面に積層して形成されか
つその周縁から離融した少なくとも第二金属膜を含み構
成されてなることを特徴とする化合物半導体装置。
An electrode made of metal films sequentially laminated on at least an active region of a compound semiconductor substrate is formed by laminating a first metal film in contact with the semiconductor substrate and a part of the upper surface of the first metal film and is spaced from the periphery thereof. A compound semiconductor device comprising at least a molten second metal film.
JP2006190A 1990-01-30 1990-01-30 Compound semiconductor device Pending JPH03225823A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2006190A JPH03225823A (en) 1990-01-30 1990-01-30 Compound semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2006190A JPH03225823A (en) 1990-01-30 1990-01-30 Compound semiconductor device

Publications (1)

Publication Number Publication Date
JPH03225823A true JPH03225823A (en) 1991-10-04

Family

ID=12016567

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2006190A Pending JPH03225823A (en) 1990-01-30 1990-01-30 Compound semiconductor device

Country Status (1)

Country Link
JP (1) JPH03225823A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100560853B1 (en) * 1997-10-06 2006-06-16 윤덕주 Silicon Wafer Surface Smoothing Method and Apparatus

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100560853B1 (en) * 1997-10-06 2006-06-16 윤덕주 Silicon Wafer Surface Smoothing Method and Apparatus

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