JPH03225833A - Manufacturing method of semiconductor device - Google Patents

Abstract

PURPOSE:To reduce the area of a bipolar element, to reduce a junction capacity and to enhance a speed and an integration by forming an inactive base, an active base and an emitter at a separate oxide film in a self-alignment. CONSTITUTION:After a first polycrystalline silicon 109, metal 110 and a first silicon oxide 111 on a laminated film of a patterned first antioxidative film 104 and an intermediate film 105, the films 104, 105 are removed, an opening is formed, a second conductivity type impurity is diffused in a semiconductor base, the impurity is diffused from the silicon 109 to form an inactive base 112A, a first conductivity type impurity is diffused in an opening except it to form an active base 115. After a second polycrystalline silicon 118 is deposited, the first impurity is diffused in the opening to form an emitter, and the base 112A, the base 115 and the emitter 120 are formed in a self-alignment manner. Thus, capacities between the base and the collector, between the collector and a substrate are reduced, and a speed and an integration are enhanced.

Description

Detailed Description of the Invention (Industrial Application Field) The present invention is a bipolar semiconductor device in which an inert base, an active base, and an emitter can be formed in a self-aligned manner with respect to an isolation oxide film. The present invention relates to a method of manufacturing the device.

(Prior Art) In fields where semiconductor integrated circuit devices require particularly high-speed operation, ECL/CML (Emitte
rCoupled Logic)/ (Curr
A bipolar semiconductor integrated circuit device based on EFLT Mode Logic is used.

When an ECL/CML circuit has constant power consumption and logic amplitude, the operating speed is determined by the elements making up the circuit, the parasitic capacitance of the wiring, the base resistance of the transistor, and the gain-bandwidth product.

Among these, to reduce parasitic capacitance, it is necessary to reduce the junction capacitance between the base and collector of transistors, which has a particularly large contribution to operating speed. It is effective to reduce the base area by drawing out the area outside the element area.

Furthermore, a method is generally employed in which a polycrystalline silicon resistor and metal wiring are formed on a thick isolation oxide film to reduce their parasitic capacitance.

On the other hand, to reduce the base resistance, it is necessary to lower the resistance of the inactive base layer and bring it as close to the emitter as possible, and to make the emitter thinner to reduce the resistance of the active base layer directly below the emitter.

Furthermore, in order to improve the gain bandwidth product, it is effective to make the emitter and base junctions shallower and to make the epitaxial layer of the collector thinner.

As a conventional technique proposed for the purpose of realizing these matters, a manufacturing method described in Japanese Patent Application No. 1983-095358 will be described.

FIGS. 2(A) to 2(F) are process cross-sectional views of the above technique.

Also, Figures 3(a) to (f) are similar to Figures 2(C) to (F
) is an enlarged view of the vicinity of the base and emitter regions for explaining in detail the steps during the process.

In addition, in Fig. 2, in order to avoid complicating the drawing,
Some membranes are omitted.

Figure 2 (A) shows that after device separation, approximately 3,000 polycrystalline silicon layers are formed, and the surface is carbonated for approximately 200 layers (not shown).
After that, a nitride film of 1,000 to 2,000 layers is selectively formed on the parts where the base electrode and the collector electrode will be formed. 201 is a P-type silicon substrate, 202 is a P-type silicon substrate
203 is an N-type epitaxial layer formed on the silicon substrate 201 and the buried diffusion layer 202. 206 is polycrystalline silicon formed on the epitaxial layer 203 and element isolation oxide film 204, 207 is polycrystalline silicon 2
This is a nitride film formed on 06.

Next, as shown in FIG. 2(B), polycrystalline silicon 20
6 is selectively oxidized to form base electrode polycrystalline silicon 206a,
206c, a collector electrode polycrystalline silicon 206d is formed. 209 is a polycrystalline silicon oxide film obtained by oxidizing the polycrystalline silicon 206.

Next, the nitride film 207 on the collector electrode is selectively removed, phosphorus ions are implanted into the collector electrode polycrystalline silicon 206d, and heat treatment is performed to form an N° type region 205 for reducing collector resistance.

Thereafter, as shown in FIG. 211D(C) and FIG. 3(a), boron ions are implanted into the base electrode polycrystalline silicon 206a and 206c through the nitride film 207 at a dose of about 1 to 5×10 cm. Annealing is performed at a temperature of about 900°C to form the base electrode polycrystalline silicon 206a.

The boron concentration in 206C is made uniform.

Next, polycrystalline silicon oxide I! The emitter formation region 209b of 1209 is selectively removed, the inner wall is oxidized, and the emitter formation region 209b of 20
An inner wall oxide film 214 having a thickness of about 0 is formed.

Further, a base electrode polycrystalline silicon 206a.

P type inert haze 210 due to diffusion from 206c
is formed.

Next, after forming an active base 211 by ion-implanting BFz to a depth of 1 to 5 XIO"CI-, as shown in FIG.
As shown in FIG. 3(b), there is an oxide film 215 of about 2,000 layers and a polycrystalline silicon layer 21 of about 2,000 layers on the entire surface.
6 is formed by CVD. In addition, in Fig. 2 (D), CVD
Oxidation lI! 215 is omitted.

Next, the polycrystalline silicon 216 is etched using reactive ion etching, and the inner wall oxide film 214 and oxide film 215 are etched.
Open the emitter as in e).

The polycrystalline silicon 216 and CVD oxide film 215 are shown in FIG.
As shown in C), an emitter that remains only on the side wall and is narrower than the opening of the nitride film 207 is opened with a self-alignment line.

At the same time, as shown in FIG. 2(E), the collector bridge polycrystalline silicon 206d is exposed.

Next, as shown in FIG. 3(d), about 3,000 layers of polycrystalline silicon 217 are deposited on the entire surface, and the surface is oxidized by about 200 layers to form an oxide film 218.
Ion implantation is performed to a depth of approximately "cm-".

Next, as shown in FIG. 3(e), the oxide film 218, polycrystalline silicon 217, and nitride film 207 are etched, and an emitter 212 is formed in the active base 211 by diffusion from the polycrystalline silicon 217 through heat treatment. .

Next, as shown in Figure 3), after removing the thin oxide films on the surfaces of the base electrode polycrystalline silicon 206a, 206c and polycrystalline silicon 217, platinum is deposited and heat treated.
Platinum silicide 219 is formed on the surfaces of base electrode polycrystalline silicon 206a, 206c and polycrystalline silicon 217.

The thin oxide film is left on the resistor and other areas that are not to be silicided, and the unreacted platinum remaining on the oxide film is removed with aqua regia. After that, there is a CVD oxide film 2 on the entire surface.
Deposit 20.

Finally, as shown in FIG. 2(F), contact holes are opened and metal electrode wiring 213 is formed.

As described above, according to the manufacturing method of the above technology, the emitter 212 is formed in the selectively oxidized region of polycrystalline silicon, and the highly doped inactive base 210 is formed by diffusion from the remaining polycrystalline silicon adjacent to this oxidized region. Therefore, the distance between the highly doped inert base 210 and the emitter 212 can be significantly reduced, and an emitter with a width narrower than the minimum design dimension can be easily formed. Since the surface of the polycrystalline silicon leading to the outside has a low resistance by silicide up to the vicinity of the emitter, the base resistance is significantly reduced.

In addition, since the width of the entire base region can be three times the minimum design dimension, the base-collector junction capacitance can be reduced, and almost all of the emitter junction is a junction with the low concentration active base 211. Coupled with the reduction in emitter width, the emitter-base junction capacitance is also reduced.

Further, since the maximum junction depth can be set to 0.3 n or less, the N-type epitaxial layer 203 can be made thin to 1 μm or less, and the collector depletion layer travel time of carriers is shortened.

In addition, due to the decrease in junction capacitance mentioned above, the collector time constant,
The emitter time constants are shortened, and these can improve the gain-bandwidth product.

In addition, as described above, the base resistance and parasitic capacitance of the transistor can be reduced and the gain bandwidth product can be improved, so that a significant increase in speed can be achieved.

(Problems to be Solved by the Invention) However, in the device having the above configuration, the pattern of the nitride film 207 and the region of the N-type epitaxial layer 203 surrounded by the isolation oxide film 204 are not self-aligned. In patterning the nitride film 207, the N-type epitaxial layer 20 is
3 had to be made larger than necessary for the operation of the element.

Therefore, with the above manufacturing method, there is a limit to the reduction of the element area, and in particular, it is impossible to sufficiently reduce the capacitance CTC between the base and collector and the capacitance CTS between the collector substrate, which is a major hindrance to achieving high speed. It became.

In addition, the existence of a limit to the reduction of the element area is a barrier to higher integration, which limits the reduction of chip size, which reduces the yield of chips from wafers and makes it impossible to reduce costs. There was a point.

Among the problems that the prior art had, this invention requires making the epitaxial layer larger than necessary, which is caused by the fact that the nitride film pattern and the epitaxial layer surrounded by the isolation oxide film are not self-aligned. point and base
The present invention provides a method for manufacturing a semiconductor device that solves the problems of the inability to reduce the capacitance between the collectors and between the collector and the substrate, which hinders speeding up, and the inability to achieve high integration.

(□ Means for Solving the Problems) In order to solve the above-mentioned problems, the present invention provides a method for manufacturing a semiconductor device in which a first acid-resistant material is patterned on one principal surface of a semiconductor substrate having a first conductivity type. Formation of a chemical film and an intermediate film After the process of depositing polycrystalline silicon, metal and first silicon oxide in Apprentice 1, and removing the first polycrystalline silicon, metal and first silicon oxide on the intermediate film In the step of forming an opening through the intermediate film and the first oxidation-resistant film, and also when diffusing the second conductivity type impurity into the opening into the semiconductor substrate, the opening is formed from the first polycrystalline silicon. a second conductivity type impurity is diffused into the opening, and a first conductivity type impurity is diffused into the other part of the opening.
This method introduces a step of diffusing a conductivity type impurity, and a step of diffusing the first conductivity type impurity from the second polycrystalline silicon after depositing the second polycrystalline silicon.

(Function) According to the present invention, since the above-described steps are introduced in the method for manufacturing a semiconductor device, the first oxidation-resistant film on the patterned first oxidation-resistant film on the semiconductor substrate and the laminated film of the intermediate film can be removed. After removing the first polycrystalline silicon, the metal, and the first silicon oxide, an opening is formed by removing the first oxidation-resistant film and the intermediate film, and a second conductivity type impurity is injected into the opening. While diffusing into the substrate, a second conductivity type impurity is diffused from the first polycrystalline silicon into the opening to form an inactive base, and a first conductivity type impurity is diffused to other openings to form an active base. do.

Further, by forming an emitter by diffusing a first conductivity type impurity into the opening after depositing the second polycrystalline silicon, the inactive base, the active base, and the emitter are formed in a self-aligned manner. Therefore, the above problem can be eliminated.

(Example) Hereinafter, an example of the method for manufacturing a semiconductor device of the present invention will be described based on the drawings. FIG. 1 is a process cross-sectional view of one embodiment of the present invention, taking a bipolar transistor as an example, and showing a process cross-section of base and emitter formation, which are important parts related to the present invention. ing. Regarding the formation of the collector, only the explanation will be given without illustration.

First, as shown in Figure 1 (al), a P-type semiconductor substrate (
(not shown), an N-type buried diffusion layer 101 is formed in the approximately In
An N-type epitaxial layer 102 is grown to a thickness of .

Approximately 100 (I
An oxide film 103 with a thickness of L is formed, and a silicon nitride film 104 with a thickness of about 2000 mm as an oxidation-resistant film, a silicon oxide film 105 with a thickness of about 10000 mm as an intermediate film, and a silicon oxide film 105 with a thickness of about 10000 mm are formed by CVD. As an oxidation-resistant film, silicon nitride films 106 having a thickness of about 3000 layers are sequentially stacked to form a stacked film.

Thereafter, a region to be an isolation region is defined using a known lamination lithography technique, and nitride silicon #106. The silicon oxide film 105 and the silicon nitride film 104 are removed by etching.

Next, as shown in FIG. 1(b), a silicon nitride film with a thickness of approximately 4,000 mm was deposited on the entire surface by CVD method, and anisotropic etching was performed. , a sidewall 107 of silicon nitride film is formed.

Next, as shown in FIG. 1(C), the oxide film 1 in the isolation region is
03 to form an oxide film 103a, the N-type epitaxial layer 102 is etched to a depth of about 3000mm, and an oxide film 108 with a thickness of about 6000mm is formed by thermal oxidation to form an N-type epitaxial layer 103a. The epitaxial layer 102 is referred to as 102a.

Next, as shown in FIG. 1(d), a photoresist (not shown) is applied, an opening is made in the photoresist in a portion (not shown) where a collector electrode will be formed, and the silicon nitride film/
Laminated film of silicon oxide film/silicon nitride film (not shown)
After removing the photoresist, a photoresist (not shown) is further applied, and the photoresist in the base electrode formation area is opened, and the silicon nitride film 106 in the base electrode formation area, the silicon nitride film sidewall 107, Then, the oxide film 103a is removed, and an oxide film 103b is formed under the silicon nitride film 104.

After removing this photoresist, approximately 30%
A layer of polycrystalline silicon 109 of 0.000000000000 is deposited, and the polycrystalline silicon 109 of the base electrode forming portion and the collector electrode forming portion is patterned by a known lithography technique using a photoresist.

After that, by using a photoresist as a mask, the polycrystalline silicon 109 in the base electrode forming part is coated with 1 to 5x
Boron ions of approximately l□+5cII-z were implanted, and lX
Phosphorus is ion-implanted in an amount of about 10"ell-".

Next, a tantalum film 110 having a thickness of approximately 1000 nm is deposited as a metal by sputtering, and a silicon oxide film 111 having a thickness of approximately 2000 nm is deposited thereon by CVD.

Next, a photoresist 112 is applied and exposed to oxygen plasma for a predetermined time to expose the surface 111a of the protruding portion of the silicon oxide film 111.

Next, the surface 111a of the silicon oxide film is etched with a hydrofluoric acid-based wet etchant, and the tantalum film 110 and polycrystalline silicon 109 are further etched by CF.

The photoresist 112 is removed by etching with a gas plasma containing as a main component to obtain a shape as shown in FIG. 1(e).

Thereafter, the base electrode forming part is covered with a photoresist (not shown), the silicon oxide film (not shown) and the tantalum film (not shown) of the collector electrode part are etched away, and this photoresist is peeled off. I'll keep it.

Next, by applying a photoresist (not shown) and using oxygen plasma, the surface of the silicon oxide film 105 is exposed as shown in FIG. Figure 1(f)
As shown in FIG. 3, the silicon oxide film 105 is removed.

Thereafter, by heat treatment in an oxygen atmosphere at approximately 800°C, boron is diffused from the polycrystalline silicon 109 into the N- type epitaxial layer 102a, forming an inert base 112A, and at the same time forming an N″ region for reducing collector resistance (Fig. (not shown) to convert the exposed surface of the polycrystalline silicon 109 into a silicon oxide film 113 and the exposed surface of the tantalum film 110 into a tantalum oxide film 114. Thereafter, the silicon nitride film 104 is plasma etched. The surface of the oxide film 103b is exposed by removing the oxide film 103b.

Next, as shown in FIG. 1(g), boron is injected into the N-type epitaxial layer 102a to an extent of 1 to 5 x 10"cm-" using an ion implantation method, and then heat-treated in an oxygen atmosphere at about 800°C. , forming an active base 115.

Next, as shown in FIG. 1(b), a silicon oxide film with a thickness of about 5,000 wafers is deposited by the CVD method, and this silicon oxide film and the silicon oxide film 103b are removed by anisotropic etching. , while opening the emitter forming portion 116, a side wall 117 of a silicon oxide film is formed.

Next, as shown in FIG. Ions are injected into the silicon 118 to an extent of about lQ''C1l-''.

Next, as shown in FIG. 1(j), the oxide film 119 and polycrystalline silicon 118 are etched to form a pattern 11.
9a and 118a are formed and heat treated at about 800° C. to form an emitter 120 by diffusion of impurities from the polycrystalline silicon 118 into the active base 115. Thus, the inert base 112A.

An active base 115 and an emitter 120 are formed in a self-aligned manner.

At this time, if the atmospheric gas contains oxygen, the sidewalls of the pattern 118a of the polycrystalline silicon 118 will also be covered by the oxide film 11.
9b is formed.

Next, as shown in FIG. 1(b), polycrystalline silicon 11
Oxide film 119a on the surface of pattern 118a of No.8.

119b is removed, and at the same time, the polycrystalline silicon oxide film (not shown) in the collector portion is also removed. Thereafter, approximately 500 layers of platinum are deposited and heat treated at 500 to 600° C. to form platinum silicide 121 on the surface of pattern 118a of polycrystalline silicon 11B.

Platinum remaining unreacted on the oxide film 119b is removed with aqua regia. After that, after depositing a CVD oxide film 122 with a thickness of about 3,000 yen, platinum silicide 121 on the emitter section, platinum silicide (not shown) on the collector section, and tantalum silicide on the base electrode! [Open a contact hole above 110.] Then, an electrode metal 123 is formed,
Use electrode wiring. In this way, a bipolar semiconductor element as a semiconductor device is manufactured.

In the above embodiment, the tantalum film 110 is formed as the metal layer formed on the polycrystalline silicon film 109 on the inert base 112A. The same effect can be achieved by using .

(Effects of the Invention) As described above in detail, according to the present invention, the inert base, active base, and emitter are formed in self-alignment with respect to the isolation oxide film, so the design is the same as that of the conventional example. Even under the standard, it is possible to significantly reduce the area of the bipolar element, and the junction capacitance C0 between the collector substrates and the junction capacitance between the base and the collector etc. can be reduced.

Furthermore, since a metal layer is formed on the base electrode polycrystalline silicon, the base resistance r is also significantly reduced.
These reductions in the junction capacitance CtS between the collector substrates, the junction capacitance CtC between the base and the collector, and the base resistance r1 are as follows:
Compared to the conventional example, it greatly contributes to lower power consumption and higher speed of bipolar semiconductor integrated circuit devices.

In addition, the reduction in element area has the effect that it is possible to achieve a significantly higher degree of integration for the same chip size as before.

[Brief explanation of drawings]

1(al) to FIG. 1(9) are process cross-sectional views for explaining one embodiment of the method for manufacturing a semiconductor device of the present invention,
FIGS. 2(^) to 2(F) are process cross-sectional views for explaining a conventional method of manufacturing a bipolar semiconductor integrated circuit device, and FIGS. 3(a) to 3(f) are Diagram (C)
FIG. 2 is an enlarged cross-sectional view of the base and emitter regions and their periphery for explaining in detail the steps shown in FIGS. 2(F) to 2(F). 102a...N-type epitaxial layer, 10B...
Oxide film, 110... Tantalum film, 111... Silicon oxide film, 112A... Inert base, 115...
Active base, 120... Emitter, 121... Platinum silicide, 122... CVD oxide film, 123...
electrode. Conventional process sectional view Fig. 2 206d, Recon conventional process sectional view Fig. 2 Detailed conventional partial process sectional view Fig. 3

Claims (1)

[Claims] (a) A first conductive layer on one main surface of a semiconductor substrate having a first conductivity type.
After forming a laminated film by laminating the oxidation-resistant film, the intermediate film, and the second oxidation-resistant film, and defining the region of this laminated film,
depositing a third oxidation-resistant film and leaving the third oxidation-resistant film only on the sidewalls of the laminated film; (b) using the laminated film in the defined area as a mask to cover the semiconductor substrate; (c) removing the second and third oxidation-resistant films and depositing first polycrystalline silicon, metal, and first silicon oxide; (d) After removing the first polycrystalline silicon, metal, and first silicon oxide present on the intermediate film, removing the intermediate film and the first oxidation-resistant film to form an opening. (e) diffusing a second conductivity type impurity into the opening into the semiconductor substrate, and diffusing a second conductivity type impurity into the opening into the semiconductor substrate via the first polycrystalline silicon; (f) forming a second silicon oxide on the sidewall of the first polycrystalline silicon of the opening; (g) ) a step of depositing a second polycrystalline silicon and diffusing a first conductivity type impurity into the semiconductor substrate through the second polycrystalline silicon.