JPH03225838A - Manufacture method of semiconductor device - Google Patents

Abstract

PURPOSE:To enable an improved mask for RIE(Reactive Ion Etching) to be formed and etching time of a semiconductor substrate to be reduced by using a resist film where an Au plating electrode is fully coated as a mask. CONSTITUTION:Au plating electrodes 3 are coated with a positive type photoresist film 4, a negative type photoresist is coated onto the positive resist film 4, and a positive resist film 5 is lamination-formed. Then, a negative resist pattern is formed between the Au plating electrodes 3 by exposure development and exposure is made from an opening 5a to the lower-layer positive resist film 4 for development. Thus, a GaAs substrate 2 is exposed between the Au plating electrodes 3 and the Au plating electrodes 3 are completely coated with the positive resist film 4 and the negative resist film 5. Further, an RIE 10 is executed with these resist films as a mask and a separated GaAs substrate 2a is formed, thus obtaining an improved mask for RIE and enabling etching time to be reduced.

Description

Detailed Description of the Invention [Objective of the Invention] (Industrial Field of Application) The present invention relates to a method of manufacturing a field effect transistor for ultra-high frequencies, and in particular, the present invention relates to a method for manufacturing a field effect transistor for ultra-high frequencies.
The present invention relates to a method of manufacturing a field effect transistor having a t5ink) structure.

(Prior art) In field effect transistors (hereinafter abbreviated as FETs) for high frequency power, in order to increase the integration density of elements, it is necessary to reduce the thermal resistance. PH5 is formed on the back side.

PH5 uses thick Au, and is similar to the second PHS.
The FET chips are separated by etching between the electrodes. Therefore, in order to manufacture chips with a good yield, 30
It is necessary to establish a technology for etching semiconductor substrates of ~40 μm.

The manufacturing process of a FET chip having an AuPH5 structure using a conventional method will be explained below using cross-sectional views of the process steps shown in FIGS. 2(a) to 2(C).

First, a semiconductor substrate 2 with an FET pattern 1 formed on its surface
After thinning to a thickness of 30 to 40 μm, an Au plating electrode 3 having a pH of 8 is formed on the back surface by selective plating (FIG. 2(a)).

Next, using the Au plating electrode 3 as a mask, the space between the electrodes is etched by RIE (reactive ion etching) 10 (FIG. 2(b)).

As a result, as shown in FIG. 2(C), the semiconductor substrate 2 is separated into a semiconductor substrate 2a, and an FET chip separated by one is completed.

(Problems to be Solved by the Invention) In the above conventional manufacturing process, as shown in FIG. 2(b), R
A PH3^U plating electrode is used as a mask for IE. ^U plating is not a good mask material for RIE, and Au is sputtered due to the sputtering effect of RIE and re-attaches to the surface to be etched, inhibiting the etching of the semiconductor substrate. For example, if the semiconductor substrate becomes arsenic. In the case of gallium, even if the RIE conditions are selected, the selectivity of gallium arsenide to Au is small and the etching rate is only 0.2μ at most.
-/It's just a win.

Therefore, it takes a long time of 200 minutes to etch a 40 μm thick GaAs substrate.

The present invention has been made to eliminate the above-mentioned drawbacks, and an object of the present invention is to provide a manufacturing method that can form a good mask for RIE and significantly shorten the etching time of a semiconductor substrate.

[Structure of the invention]

(Means for Solving the Problems) A method for manufacturing a semiconductor device according to the present invention includes the steps of forming a plurality of electrodes made of gold with a thickness of 10 μm or more on a semiconductor substrate, and applying photoresist over the entire surface of the semiconductor substrate. and forming a continuous first photoresist film from above the electrodes to between the electrodes.

a step of laminating a second photoresist film on the first photoresist film so that holes are formed between the electrodes;
removing the photoresist film leaving only the portions facing the upper and side surfaces of the electrodes; and performing dry etching between the electrodes using the first and second photoresist films as masks. Features.

(Function) When dry etching a semiconductor substrate from between a plurality of Au plated electrodes, the present invention uses a resist film that completely covers the Au plated electrodes as a mask, compared to the conventional method in which the Au plated electrodes are used as a mask. Since this method is used, a high selectivity to the semiconductor substrate can be achieved, and the etching time can be significantly shortened.

(Example) Hereinafter, one embodiment of the present invention will be described with reference to the drawings.

FIGS. 1(a) to 1(f) are cross-sectional views showing, in order of steps, a method for manufacturing an FET using gallium arsenide (hereinafter referred to as GaAs) for a semiconductor substrate.

As shown in FIG. 1(a), a GaAs semi-insulating substrate 2
After forming the FET pattern 1 on the surface, lapping and chemical polishing were performed on the back surface of the GaAs substrate to reduce the substrate thickness to 40 mm.
The Au plated electrode 3 having a pH of 5 is formed on the back surface of this GaAs substrate by selective plating to a thickness of 30 μm.

Next, this Au plated electrode 3 is coated with a positive type photoresist film (FIG. 1(b)). In order to completely cover the 30 μm thick Au plated electrode, LP is used to form the positive resist film 4. -10 (trade name: Hoechst), and the film thickness was set to 10 μm.

Next, a negative type photoresist, for example, OMR (trade name Nitoki Ohka) is applied on the positive resist film 4,
A negative resist film 5 is formed in layers. Then, a negative resist pattern having openings narrower than the electrode spacing is formed between the Au-plated electrodes 3 by exposure and development (FIG. 1(C)).

Next, the positive resist film 4 below the openings 5a of the negative resist pattern is exposed and developed. At this time, the openings 5a of the upper layer negative resist film are not affected at all by the exposure and development of the positive resist film 4, and conversely serve as a mask during the exposure and development of the positive resist film 4 to open the negative resist film. The amount of underetching from the hole 5a can be suppressed to a small level. Therefore, the 10 μm thick positive resist film 4 can be patterned so that the side surface of the Au-plated electrode 3 remains (FIG. 1(d)).

As a result, the GaAs substrate 2 is exposed between the Au plating electrodes 3, and the Au plating electrodes 3 are completely covered with the positive resist film 4 and the negative resist film 5. Therefore, RIE 10 was performed using these resist films as a mask, and the GaAs substrate 2 between the U plating electrodes 3 was etched, and the separated G
An aAs substrate 2a is formed (FIG. 1(e)).

According to the above method, since RIE is performed using a resist film as a mask, there is no exposed part of Au compared to the conventional method using a conventional Au plating electrode as a mask. There's nothing to do. Therefore, a high selectivity to the GaAs substrate can be achieved, and the etching time can be kept to about one hour. Therefore.

Etching time for GaAs substrates can be significantly shortened.

Next, by dissolving and removing the positive resist film 4 and the negative resist film 5, one separated FET chip is completed (FIG. 1(f)).

〔Effect of the invention〕

As described above, according to the present invention, a thick Au-plated electrode can be completely covered with a resist film, so that RI
It is possible to provide a good mask against E.

Therefore, compared to the conventional method in which the Au-plated electrode is used as a mask, the etching time can be significantly shortened, and FET chips can be separated with a high yield.

[Brief explanation of drawings]

FIGS. 1(a) to (f) are cross-sectional views showing the FET manufacturing method according to the present invention in the order of steps, and FIGS. 2(a) to (c)
) are cross-sectional views showing the conventional FET manufacturing method in order of process.

Claims (1)

[Claims] A step of forming a plurality of electrodes made of gold with a thickness of 10 μm or more on a semiconductor substrate, and applying a photoresist to the entire surface of the semiconductor substrate to form a continuous first photoresist film from above the electrodes to between the electrodes. a step of laminating a second photoresist film on the first photoresist film so that holes are formed between the electrodes; The method includes the steps of removing the photoresist film leaving only the portions facing the upper and side surfaces of the electrodes, and performing dry etching between the electrodes using the first and second photoresist films as masks. A method for manufacturing a semiconductor device.