JPH03225870A - Manufacture of heterojunction bipolar transistor - Google Patents

Abstract

PURPOSE:To realize high performance and high reliability by forming a second semiconductor layer to become the base layer, wherein the hand gap is narrower than that of a first semiconductor layer, on an insulating layer, and then forming first and third semiconductor layers to become emitter layers on the second semiconductor layer. CONSTITUTION:Trenches 42 formation and insulating film 8 burying are performed in advance at the unnecessary parts of a first semiconductor layer, whereby a wafer 3, in which the element region is limited in the condition that it is flattened with this, can be gotten. And a second semiconductor layer to become a base layer 9, wherein the hand gap is narrow, is formed on this wafer 3, subsequently a third semiconductor layer to become an emitter layer 10 is made. Accordingly, base-collector junction area is reduced to an irreducible minimum value, and surface condition where there is no irregularity can be gotten. Hereby, high performance and high reliability can be realized for an ultra small heterojunction bipolar transistor.

Description

DETAILED DESCRIPTION OF THE INVENTION [Objective of the Invention (Field of Industrial Application)] Sadaaki Ki is concerned with the production of ultra-small heterojunction bipolar transistors.

(Prior Art) Heterojunction bipolar transistors have attracted attention as having high performance, and research and development of heterojunction bipolar transistors using compound semiconductors has been particularly active. In recent years, technological development has been progressing to introduce heterojunctions into silicon-based bipolar transistors as well. Some of the silicon-based heterojunction bipolar transistors that have been reported so far include, for example, the Kozumono (19881EDM DjgestorTcc) shown in Figure 4.
hnical Papcrs, p, 566,
J.F.

G 1bbons, ct al) and those shown in Figure 5 (1989Symp, VLS) Tech, Dig
cstorTechnicalPapers, p.
95. G, L, PaLLon et at). All of these use silicon as a base layer, which is a strained epitaxial layer with a narrower bandgap than silicon.
A germanium alloy layer is used.

In the device shown in FIG. 4, the n-type silicon layer 4 serves as the collector layer.
A p-type silicon-germanium alloy layer 43 serving as a base layer and an n-type silicon layer 44 serving as an emitter layer are sequentially epitaxially grown on the entire surface of 2. After the epitaxial growth process, a p-type base layer 45 is formed by diffusion, and then the area around the device region is removed by mesa etching.

In the device shown in FIG. 5, an n-type silicon layer 53 serving as a collector layer is formed by epitaxial growth via an n-type buried layer 52, and an insulating film 56 surrounding the device region is patterned thereon. Then, the insulating film 5 is inserted from the element head mounting opening.
A p+ type polycrystalline silicon layer 57, which will become a base extraction electrode, is patterned so as to extend over the base lead-out electrode, and then a p-type silicon-germanium alloy layer 54, which will become a base layer, is formed by epitaxial growth. An emitter opening is formed and a polycrystalline silicon emitter layer 55 is formed.

However, each of these conventional silicon-based heterojunction bipolar transistors has the following drawbacks.

In the device of FIG. 4, the collector layer 42 of the external base layer 45
The junction area with the transistor is large, and the collector-base junction capacitance, which affects the switching time of the transistor, is large. In the device shown in FIG. 5, the device area is limited by the insulating film 56, so compared to the device shown in FIG.
Collector junction capacitance can be reduced. However, since a step difference (unevenness) is formed in the emitter region, problems such as breakage of the electrode wiring arise. Furthermore, since the distance between the polycrystalline silicon serving as the base extraction electrode and the intrinsic GB region of the transistor is determined by the mask dimensions, controllability is poor, and as this distance increases, the base resistance also increases.

(Problem to be solved by the invention) As described above, in the silicon-based T7 bipolar transistor proposed so far, sufficient performance can be achieved due to the large base-collector junction capacitance.
Another problem is that it is difficult to achieve high reliability due to large irregularities on the surface of the transistor, and it is difficult to keep the base resistance low.

An object of the present invention is to provide a method for manufacturing a heterojunction bipolar transistor that can solve these problems and achieve high performance and high reliability.

[Structure of the Invention (Means for Solving the Problems) A method for manufacturing a heterojunction bipolar transistor according to the present invention includes: forming a first semiconductor layer of a first conductivity type to serve as a collector layer on a substrate; forming a groove by selectively etching an unnecessary portion of the semiconductor layer, and filling the groove with an insulating film; The method is characterized by comprising six steps: forming a second semiconductor layer to become an emitter layer; and forming a third semiconductor layer of the first conductivity type to become an emitter layer on the second semiconductor layer.

(Function) According to the first aspect of the present invention, grooves are formed and an insulating film is buried in an unnecessary portion of the first semiconductor layer which becomes the collector layer in advance;
As a result, a wafer with a limited device area in a flattened state can be obtained. Then, a second semiconductor layer that will become a base layer with a narrow band gap is formed on this wafer, and then a third semiconductor layer that will become an emitter layer is formed. Therefore, the base-collector junction area is reduced to the minimum necessary value, and a surface condition free of irregularities can be obtained. As described above, it is possible to improve the performance and reliability of an ultra-small heterojunction bipolar transistor.

(Example) The present invention will now be described in detail.

FIGS. 1(a) to 1(p) show the manufacturing process of an embodiment in which the present invention is applied to a silicon-based heterojunction bipolar transistor. After forming an n-type layer 2 which will become a collector buried layer by doping As on the surface of a p-type silicon single crystal substrate 1, an n-type layer which will become a collector layer is epitaxially grown (see FIG. 1(a)). )). rl type layer 3 has a thickness of 400 mm
Assume 0 people. Next, a reactive ion etching method using a resist mask is used to form an element isolation region with a depth of about 4 mm to reach the substrate 1. Groove 4. A silicon oxide film 6 is formed on the inner and outer surfaces of the n-type layer 3 by thermal oxidation. In order to prevent inversion, a p+ type layer 5 is formed by boron ion implantation at the bottom of the 4-square area (FIG. 1(b)).

A polycrystalline silicon layer 7 is buried in the element isolation trench 4□ (FIG. 1(C)).

Next, the area around the n'' type layer 3 is removed by selective etching, leaving only the portions necessary for the element region and the collector extraction region, to form a full 4□ area (FIG. 1(d)).
). Then, a silicon oxide film 8 is deposited on the entire surface by the CVD method, the surface is flattened with a resist, etc., and then etched and hacked to form a silicon oxide film 8 buried in a full area.
The silicon oxide film 6 on the surface of the n-type layer 3 is removed by etching (FIG. 1(e)).

A p-type, Likosi-Kermanium alloy layer 9, which will serve as a base layer, is epitaxially grown on the n-thirium 3 and the surrounding silicon oxide film 8 of the wafer thus flattened (first diagram ``)''). For example, using the molecular beam epitaxy method, a p-type silicon/rumanium alloy layer 9 is formed as a strained epitaxial layer having 2006 k of germanium while doping B to 1,000 k. The B concentration is ] X 1.1) Approx. Next, 500 layers of emitter layer 10 (11 n-type cells) were formed to form an emitter knee tactile layer.
− type silicon layer 11′, [j [−10 people, Ill
ll Table of Contents Evitanyal is grown (Figure 1 (g)). For example, the n-type silicon layer 10 contains As]\I Ll i
8,,,/cm (concentration of n'-type hormone 1 m
11. ! : Similarly, As is I x 1020/'cm
' shall include.

On the top, a silicon oxide film 12 is deposited by CVD method [
2. Add this to the emitter area using the reactive IT fetch jig method using a 7-stroke mask (unexpectedly).
(Remove the f-ching, then continue with the n-type
layer ', ] is selectively removed (FIG. 1(h)).

Note that the process diagrams from FIG. 1(h) onward show the main parts of the previous process diagrams in an enlarged manner. Thereafter, a silicon oxide film 13 is deposited again on the entire surface by the CVD method, and this is etched on the entire surface using the reactive ion etching method, leaving only the silicon oxide film 12 and the side walls of the n-type silicon layer 11. Thereafter, B is ion-implanted using the silicon oxide films 12 and 13 as masks to form a p-type layer 14, which will become an external base layer, at a depth that reaches the n-type layer 3 (FIG. 1(i)). Then, the silicon oxide films 12 and ]3 are removed by etching, and a resist mask (not shown) covering the emitter region and the base lead-out region is formed by turning the silicon layers ]0 and ]3, which have been converted into p" type layers. The underlying silicon-kermanium alloy layer 9 is removed by etching (FIG. 1(j)).

The p-type layer 4 patterned in this way functions as an external base layer in the area surrounded by the silicon oxide film 8, and extends on the silicon oxide film 8 (the Y-shaped part functions as a base extraction electrode). do.

Thereafter, the emitter vines and base region are covered with a resist mask 15, and As is ion-implanted to form an n-type layer 16 for extracting the collector to a depth that reaches the n+-type layer 2 (FIG. 1(k)). . After removing the resist mask 15, a silicon oxide film 17 is deposited by the CVD method, and selectively etched to form emitter, base, and collector electrode openings 18, 19, and 2o (Figure ¥51).
g)). Finally, metal electrodes 21, 22 and 23 such as AΩ
(Fig. 1(m)).

Figures 2 and 3 are A-A in Figure 1(m), respectively.
' and the impurity concentration distribution at the BB' position.

As described above, according to this embodiment, a groove is dug in the unnecessary part of the wafer on which the rl type layer 3 serving as the collector layer is formed, and the oxide film 8 is buried therein and flattened. A silicon alloy layer 9 serving as a base layer and a silicon layer 1o serving as an emitter layer are sequentially grown by epitaxial growth. Therefore, since the regions necessary for the emitter and base of the device are narrowly limited by the buried oxide film, the base-collector junction capacitance does not become large as in the conventional structure shown in FIG. Furthermore, as is clear from the comparison with the conventional structure shown in FIG. 5, the flatness of the wafer is excellent, and there are no large irregularities in the electrode extraction portion.

Furthermore, the extrinsic base region can be brought close to the transistor intrinsic region and can be flattened to sufficiently reduce the base resistance.

As a result of the above, a high performance and highly reliable heterojunction bipolar transistor can be obtained.

The present invention is not limited to the above embodiments.

For example, it is possible to change the amount of germanium a in the silicon alloy layer in the thickness direction, and in that case, the content distribution can be made to be inclined in the depth direction. Furthermore, although the embodiments have described silicon-based heterojunction bipolar transistors, it is also possible to similarly apply the present invention to the production of bipolar transistors by heteroepitaxial growth using other semiconductor materials. In addition, in the embodiment, a silicon oxide film is used as the insulating film, or a silicon nitride film or the like can be used as necessary.Furthermore, in the embodiment, an emitter junction is used.

Although the transistor in which both the collector junction and the collector junction are heterojunctions has been described, the present invention is also effective in cases where only one of the collector junctions is a heterojunction.

[Effects of the Invention] As stated above, according to the present invention, an ultra-compact, high-performance, and highly reliable heterojunction hyperpolar transistor 7 transistor is created by utilizing insulating film embedding technology and heteroepitaxial technology. can be obtained.

[Brief explanation of drawings]

Figures 1 (a) to (m) are diagrams showing the manufacturing process of a heterojunction bipolar transistor according to an embodiment of the present invention, and Figure 2 shows the impurity concentration distribution in the AA' cross section of Figure 1 (Ill). The figure shown in Figure 13 also shows the impurity concentration of the BB' cross section in Figure 1 (m)! Figure 4 is a diagram showing a conventional heterojunction bipolar transistor; Figure 5 is a diagram showing another conventional heterojunction bipolar transistor; 1...p-type silicon substrate, 2...n-type layer (collector buried layer), 3...n-type layer (collector layer), 41
．． 42...Groove, 5...p+ type layer, 6...silicon oxide film, 7...polycrystalline silicon layer, 8...silicon oxide film, 9...p type silicon germanium alloy layer (base layer), 10... n-type layer (emitter layer), 11...
n-type layer (emitter contact layer), 12... silicon oxide film, 13... silicon oxide film, 14... p-type layer (external base layer), 15... resist mask, 1
6... n-type layer collector extraction layer), 17... silicon oxide film, 18.19.20... electrode opening, 21, 2
2.23... Electrode.

Claims (2)

[Claims] (1) A step of forming a first semiconductor layer of a first conductivity type to serve as a collector layer on a substrate, selectively etching an unnecessary portion of the first semiconductor layer to form a groove, and forming an insulating film in the groove. a step of embedding, a step of forming a second semiconductor layer serving as a base layer with a band gap smaller than that of the first semiconductor layer on the first semiconductor layer and the insulating film around the first semiconductor layer; A method for manufacturing a heterojunction bipolar transistor, comprising the step of forming a third semiconductor layer of a first conductivity type to serve as an emitter layer on the semiconductor layer. (2) forming a first conductivity type first semiconductor layer to serve as a collector layer on the substrate; selectively etching an unnecessary portion of the first semiconductor layer to form a groove; and forming a first semiconductor layer in the groove; a step of embedding an insulating film; a step of forming a second semiconductor layer serving as a base layer having a narrower bandgap than the first semiconductor layer on the first semiconductor layer and the surrounding insulating film; a step of sequentially forming a third semiconductor layer of the first conductivity type to serve as an emitter layer and a fourth semiconductor layer of the first conductivity type to serve as an emitter contact layer on the surface of the semiconductor layer; patterning a second insulating film covering the emitter region thereon, and selectively etching the fourth semiconductor layer using the second insulating film as a mask; and etching the fourth semiconductor layer and the second insulating film. a step of selectively forming a third insulating film on the side wall of the stack; and a step of ion-implanting impurities using the second and third insulating films as masks to form an external base layer of a second conductivity type. A method for manufacturing a heterojunction bipolar transistor, comprising: