JPH03225928A - Epitaxial growth method and semiconductor device - Google Patents

Epitaxial growth method and semiconductor device

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Publication number
JPH03225928A
JPH03225928A JP2176690A JP2176690A JPH03225928A JP H03225928 A JPH03225928 A JP H03225928A JP 2176690 A JP2176690 A JP 2176690A JP 2176690 A JP2176690 A JP 2176690A JP H03225928 A JPH03225928 A JP H03225928A
Authority
JP
Japan
Prior art keywords
epitaxial growth
substrate
compound semiconductor
semiconductor device
orientation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2176690A
Other languages
Japanese (ja)
Inventor
Shigeo Goshima
五島 滋雄
Kazuhiro Mochizuki
和浩 望月
Yasunari Umemoto
康成 梅本
Shinichiro Takatani
信一郎 高谷
Tomonori Tagami
知紀 田上
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Hitachi Ltd
Original Assignee
Hitachi Ltd
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Filing date
Publication date
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Priority to JP2176690A priority Critical patent/JPH03225928A/en
Publication of JPH03225928A publication Critical patent/JPH03225928A/en
Pending legal-status Critical Current

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  • Recrystallisation Techniques (AREA)
  • Junction Field-Effect Transistors (AREA)
  • Physical Deposition Of Substances That Are Components Of Semiconductor Devices (AREA)

Abstract

PURPOSE:To obtain a method for epitaxially growing an InGaAs layer which can be grown at a high temperature, is excellent in surface flatness and is high in carrier concentration by growing a thin film crystal having composition elements different from those of a substrate by means of using compound semiconductor single crystal substrates having surface orientations tilted from a low index surface in a desired direction. CONSTITUTION:Substrates with orientations of the face 100 and those tilted from the face 100 to a orientation [011] and an orientation [011] by 2 deg., 3 deg., 5 deg. are used as GaAs substrates to be used for epitaxial growth, and molecular beam epitaxy(MBE) method is used to grow InxGa1-xAs (x=0.2) having a lattice constant different from that of the substrate by a thickness of 2mum. Substrate temperature at this time is 650 deg.C. As an off-angle increases, an island defect is rapidly reduced until the island defect completely disappears with an off-angle of 5 deg. both in the orientation [011] and in the orientation [011] so that an extremely flat crystal surface without an island defect can be obtained.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、表面平坦性が良好かつ不純物を高濃度にドー
ピング可能な半導体結晶のエピタキシャル成長法及びこ
のエピタキシャル成長法を用いて製造した半導体装置に
関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for epitaxially growing a semiconductor crystal that has good surface flatness and can be doped with impurities at a high concentration, and a semiconductor device manufactured using this epitaxial growth method.

〔従来の技術〕[Conventional technology]

従来、GaAs基板上にInGaAs層を有する電3− 界効果トランジスタ等の電子素子については、ジャーナ
ル・オブ・バキューム・サイエンス・アンド・テクノロ
ジー B6,620 (1988年)(J、 Vac、
 Sci、 Technol、 B6  (2) 62
0゜1988)において論じられている。この記載によ
れば基板温度560℃以上でInGaAs層を成長する
と、Inの再蒸発及びモホロジーの劣化が生ずる。
Conventionally, electronic devices such as field effect transistors having an InGaAs layer on a GaAs substrate have been described in Journal of Vacuum Science and Technology B6, 620 (1988) (J, Vac,
Sci, Technol, B6 (2) 62
0°1988). According to this description, when an InGaAs layer is grown at a substrate temperature of 560° C. or higher, re-evaporation of In and deterioration of morphology occur.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

上記従来技術は、基板結晶面を(100)としているた
め1次に記す問題があった。
In the above-mentioned conventional technology, since the substrate crystal plane is (100), there is a problem described in the first order.

1 、0aAs (100)面上にInGaAsをエピ
タキシャル成長する場合、基板温度560℃以上ではI
nの再蒸発が生じるため、高温での結晶成長が不可能で
あった。
1, 0aAs When InGaAs is epitaxially grown on the (100) plane, I
Crystal growth at high temperatures was not possible due to the re-evaporation of n.

2、GaAs (100)面上にInGaAsを形成す
る場合、In混晶比又は膜厚の増加に伴い表面平坦性が
低下するという問題があった。
2. GaAs When InGaAs is formed on the (100) plane, there is a problem that the surface flatness decreases as the In mixed crystal ratio or film thickness increases.

3、GaAs (100)面上に形成したInGaAs
に不純物原子としてSiのデルタドーピングを行4 なうと、キャリアの活性化率は60%程度までしか上げ
ることができなかった。
3. InGaAs formed on GaAs (100) plane
When delta doping with Si as an impurity atom was performed, the carrier activation rate could only be increased to about 60%.

さらに、従来のエピタキシャル層を用いて半導体装置を
製造するとエピタキシャル層が平坦でないため、微細な
半導体素子を所望の形状に形成することが困難であると
いう問題があった。また、キャリア濃度が小さいため、
半導体素子の電流利得が向上しないという問題があった
。
Furthermore, when a semiconductor device is manufactured using a conventional epitaxial layer, there is a problem in that it is difficult to form a fine semiconductor element into a desired shape because the epitaxial layer is not flat. In addition, since the carrier concentration is small,
There was a problem that the current gain of the semiconductor element was not improved.

本発明の目的は、高温成長可能な、表面平坦性に優れた
、キャリア濃度が高濃度のInGaAs層のエピタキシ
ャル成長法を提供することにある。
An object of the present invention is to provide a method for epitaxially growing an InGaAs layer that can be grown at high temperatures, has excellent surface flatness, and has a high carrier concentration.

本発明の第2の目的は、InGaAs層を有し、電流利
得の向上した半導体素子を有する半導体装置を提供する
ことにある。
A second object of the present invention is to provide a semiconductor device having a semiconductor element having an InGaAs layer and improved current gain.

〔課題を解決するための手段〕[Means to solve the problem]

上記目的は、(1)低指数面から所望の方向に傾けた表
面面方位を有する化合物半導体単結晶基板を用い、該基
板とは異なる構成元素を有する薄膜結晶を成長させるこ
とを特徴とするエピタキシャル成長法、(2)表面面方
位を低指数面から傾けた化合物半導体単結晶基板を用い
、該基板表面に形成された原子ステップ列に対しての付
着係数が低指数面での付着係数に比して大きい元素を少
なくとも構成元素として含む化合物半導体を成長させる
ことを特徴とするエピタキシャル成長法、(3)低指数
面から所望の方向に傾けた表面面方位を有するm−v族
化合物半導体単結晶基板上に少なくともInを構成元素
として含む化合物半導体薄膜を成長させることを特徴と
するエピタキシャル成長法、(4)上記化合物半導体薄
膜は、(In、Ga)Asである上記3記載のエピタキ
シャル成長法、(5)上記表面面方位は上記低指数面か
ら2度以上傾いていることを特徴とする上記1.2又は
3記載のエピタキシャル成長法によって達成される。
The above object is (1) epitaxial growth characterized by using a compound semiconductor single crystal substrate having a surface plane tilted in a desired direction from a low index plane and growing a thin film crystal having constituent elements different from that of the substrate; (2) Using a compound semiconductor single crystal substrate whose surface orientation is tilted from a low-index plane, the adhesion coefficient for the atomic step array formed on the substrate surface is compared to the adhesion coefficient for the low-index plane. (3) an epitaxial growth method characterized by growing a compound semiconductor containing at least a large element as a constituent element; an epitaxial growth method characterized by growing a compound semiconductor thin film containing at least In as a constituent element, (4) an epitaxial growth method according to the above 3, wherein the compound semiconductor thin film is (In, Ga) As; (5) an epitaxial growth method according to the above This is achieved by the epitaxial growth method described in 1.2 or 3 above, wherein the surface plane orientation is inclined by 2 degrees or more from the low index plane.

上記第2の目的は、(6)上記1から5までのいずれか
に記載のエピタキシャル成長法により成長してなる化合
物半導体薄膜を有することを特徴とする半導体装置、(
7)表面面方位を低指数面から傾けた化合物半導体単結
晶基板上に、該基板の構成元素とは異なる構成元素を有
するエピタキシャル成長層を設け、該エピタキシャル成
長層上に、半導体素子の少なくとも一部分が配置された
ことを特徴とする半導体装置、(8)表面面方位を低指
数面から傾けた化合物半導体単結晶基板上に、該基板の
格子定数とは異なる格子定数を有するエピタキシャル成
長層を設け、該エピタキシャル成長層上に、半導体素子
の少なくとも一部分が配置されたことを特徴とする半導
体装置、(9)表面面方位を低指数面から傾けたm−v
族化合物半導体単結晶基板上に、少なくともInを構成
元素として含むエピタキシャル成長層を設け、該エピタ
キシャル成長層を不純物を有することを特徴とする半導
体装置、(10)上記不純物は、上記エピタキシャル成
長層の一原子面に存在することを特徴とする上記9記載
の半導体装置、(11)上記エピタキシャル成長層は、
上記半導体素子の能動層として配置されたことを特徴と
する上記7から10のいずれかに記載の半導体装置によ
って達成される。
The second object is (6) a semiconductor device comprising a compound semiconductor thin film grown by the epitaxial growth method according to any one of 1 to 5 above;
7) An epitaxial growth layer having a constituent element different from that of the substrate is provided on a compound semiconductor single crystal substrate whose surface orientation is inclined from a low index plane, and at least a portion of a semiconductor element is disposed on the epitaxial growth layer. (8) A semiconductor device characterized in that: (8) an epitaxial growth layer having a lattice constant different from that of the substrate is provided on a compound semiconductor single crystal substrate whose surface orientation is inclined from a low index plane; A semiconductor device characterized in that at least a portion of a semiconductor element is disposed on a layer, (9) an m-v surface plane tilted from a low index plane;
A semiconductor device characterized in that an epitaxially grown layer containing at least In as a constituent element is provided on a group compound semiconductor single crystal substrate, and the epitaxially grown layer has an impurity, (10) the impurity is present in one atomic plane of the epitaxially grown layer. 9. The semiconductor device according to 9 above, wherein the epitaxial growth layer is:
This is achieved by the semiconductor device according to any one of items 7 to 10 above, which is arranged as an active layer of the semiconductor element.

− 〔作用〕 結晶基板表面を低指数面から傾けると原子ステップ列が
形成される。ステップ列に構成元素又は不純物原子が置
換し易いため、オフ角度が大きくなればより置換し易く
、テラス面における2次元核生成の確率が減少する。す
なわち、ステップ列では、構成原子のダングリングボン
ドの配置関係が低指数面上とは異なるため、エピタキシ
ャル成長に供される構成原子及び不純物原子の付着係数
及び置換位置が変化する。付着係数及び置換位置の変化
は、オフ角度の増大と共に大きくなるため、テラス面で
の2次元核生成の確率が減少し、かつ不純物はステップ
列で格子位置に置換し易くなる。
- [Operation] When the crystal substrate surface is tilted from the low index plane, an atomic step array is formed. Since constituent elements or impurity atoms are easily substituted in the step row, the larger the off angle, the easier the substitution, and the probability of two-dimensional nucleation on the terrace surface is reduced. That is, in the step row, the arrangement relationship of dangling bonds of the constituent atoms is different from that on the low index plane, so the adhesion coefficients and substitution positions of the constituent atoms and impurity atoms subjected to epitaxial growth change. Changes in the adhesion coefficient and the substitution position increase as the off-angle increases, so the probability of two-dimensional nucleation on the terrace surface decreases, and impurities are more likely to be substituted at the lattice positions in the step sequence.

これにより結晶表面の平坦性、不純物の活性化率が向上
する。
This improves the flatness of the crystal surface and the activation rate of impurities.

〔実施例〕〔Example〕

実施例1 以下、本発明の第1の実施例を説明する。エピタキシャ
ル成長に供するG a A s基板として面方位を(1
00)面及び(100)面から2度、3度、8− 5度各々(011)方向及び(011)方向に傾けたも
のを用いて、分子線エピタキシー(MBE法)により、
上記基板と格子定数の異なる格子定数を有するI nx
Gal−xAs (x = 0 、2 )を膜厚2μm
成長する。この時の基板温度は650℃である。
Example 1 A first example of the present invention will be described below. As a GaAs substrate for epitaxial growth, the plane orientation is (1
By molecular beam epitaxy (MBE method) using planes tilted 2 degrees, 3 degrees, and 8-5 degrees from the (00) and (100) planes in the (011) direction and (011) direction, respectively,
Inx having a lattice constant different from that of the above substrate
Gal-xAs (x = 0, 2) with a film thickness of 2 μm
grow up. The substrate temperature at this time was 650°C.

(100)面(オフ角度O度)の基板を用いた試料では
、走査電子顕微鏡観察の結果、105個/cI112の
島状欠陥がウェハ全面に発生したが、オフ角度を増大す
るに従って島状欠陥は、急激に減少し、(011)方向
、(011)方向ともオフ角度5度では島状の欠陥は完
全に消滅し、極めて平坦な島状欠陥の存在しない結晶表
面が得られた。
In a sample using a substrate with a (100) plane (off angle of 0 degrees), as a result of scanning electron microscopy observation, 105/cI112 island-like defects were generated on the entire wafer surface, but as the off-angle increases, island-like defects decreased rapidly, and at an off-angle of 5 degrees in both the (011) direction and the (011) direction, the island-like defects completely disappeared, and an extremely flat crystal surface free of island-like defects was obtained.

実施例2 本発明の第2の実施例を第1図により説明する。Example 2 A second embodiment of the present invention will be explained with reference to FIG.

MBE法により、InGaAsを形成する場合、基板温
度580℃以上では、Inの付着係数が低下する。第1
図は、付着係数を1とした場合にI nxcx a、−
x A sのIn組成Xが0.1となる成長条件で作製
したInGaAsのIn組成を示す。600℃では、通
常の(100)GaAs基板を用いた場合Xは0.01
5と約15%まで低下している。
When forming InGaAs by the MBE method, the adhesion coefficient of In decreases when the substrate temperature is 580° C. or higher. 1st
The figure shows that when the adhesion coefficient is 1, I nxcx a, -
The In composition of InGaAs produced under growth conditions such that the In composition X of x As is 0.1 is shown. At 600°C, when using a normal (100) GaAs substrate, X is 0.01
5, which is about 15%.

これに対し、(100)面から(011)方向に基板表
面を傾斜させ、オフ角度を大にするとIn組成は増大の
傾向を示す。
On the other hand, when the substrate surface is inclined from the (100) plane to the (011) direction and the off angle is increased, the In composition tends to increase.

基板温度580℃においては、(100)面(オフ角度
O度)では、70%弱の付着率であるが、5度オフでは
95%まで増大する。
At a substrate temperature of 580° C., the adhesion rate is a little less than 70% on the (100) plane (off angle 0 degrees), but increases to 95% when the off angle is 5 degrees.

一般に、化合物半導体では、基板温度を低下すると移動
度が減少する。本発明では、580℃程度の高温成長に
おいても、In組成の減少を抑えられるため、高温成長
が可能であり、高移動度のInGaAsが得られた。
Generally, in compound semiconductors, the mobility decreases when the substrate temperature is lowered. In the present invention, even in high-temperature growth of about 580° C., the decrease in In composition can be suppressed, so high-temperature growth is possible, and InGaAs with high mobility can be obtained.

実施例3 以下、本発明の第3の実施例としてInGaAsにn型
不純物としてSiをデルタドーピングし、高濃度の薄膜
をエピタキシャル成長する方法について説明する。
Embodiment 3 Hereinafter, as a third embodiment of the present invention, a method of delta-doping InGaAs with Si as an n-type impurity and epitaxially growing a highly concentrated thin film will be described.

まず、(100)面から(011)方向に傾斜させた表
面を有する半絶縁性G a A s基板に、硫酸系の化
学エツチングを施す。次に、分子線エピタキシー(MB
E)装置に基板を装置した後、580〜650℃でAS
4ビームを基板表面に照射しながら、加熱する。次に基
板温度を500℃に降温しエピタキシャル成長を開始す
る。エピタキシャル成長は、原料のGaのシャッターを
開き、まずアンドープGaAsを3000Å以上堆積し
、さらにInのシャッターを開き、InGaAs (I
n組成0.1)を250人堆積した。次にGa、 In
シャッターを閉じ、Siシャッターを開く。Si面密度
がI X 1013cm−”となるまでSiを照射した
後、Siシャッターを閉じ、Ga、Inシャッターを開
いてアンドープInGaAsを250人堆積し、さらに
Inシャッターを閉じアンドープGaAsを1000人
積層0た。
First, a semi-insulating GaAs substrate having a surface inclined from the (100) plane to the (011) direction is subjected to sulfuric acid-based chemical etching. Next, molecular beam epitaxy (MB
E) After installing the substrate in the device, AS at 580-650℃
The substrate surface is heated while being irradiated with four beams. Next, the substrate temperature is lowered to 500° C. and epitaxial growth is started. In epitaxial growth, a shutter of Ga as a raw material is opened, undoped GaAs is deposited to a thickness of 3000 Å or more, and a shutter of In is opened to deposit InGaAs (I).
n composition 0.1) was deposited by 250 people. Next, Ga, In
Close the shutter and open the Si shutter. After irradiating Si until the Si surface density becomes I x 1013 cm-'', the Si shutter is closed, the Ga and In shutters are opened to deposit 250 layers of undoped InGaAs, and then the In shutter is closed and 1000 layers of undoped GaAs are deposited. Ta.

第2図は、上記方法で作製したデルタドープInGaA
sのオフ角度依存性を示す図である。
Figure 2 shows delta-doped InGaA prepared by the above method.
FIG. 3 is a diagram showing the off-angle dependence of s.

(100)面から(011)方向及び(011)方向に
5度傾斜した場合、(100)面の試料に比してキャリ
アの面密度が、20%程度増大して11− いる。
When the sample is tilted by 5 degrees from the (100) plane to the (011) direction and the (011) direction, the carrier areal density increases by about 20% (11-) compared to the (100) plane sample.

実施例4 以下、本発明の半導体装置の製造について説明する。第
3図は、電界効果トランジスタの断面図である。(10
0)面から(011〕方向に5度傾斜させた半絶縁性G
 a A s基板1上にMBE法により、アンドープG
aAs2 (500nm)、アンドープIno、□Ga
o、、As層3(10nm)を順次積層する。アンドー
プI n、、1Gao、、As層層中中は、I X 1
0 ”cm−2のSLデルタドープ層3′を挿入しであ
る。さらに、MBE法でアンドープG a A s層4
(10nm)及びアンドープAflGaAs層5(20
nm)を積層する。続いて通常のホトリソグラフィー工
程とドライエツチング工程によりアンドープG a A
 s層4及びアンドープAflGaAs層5を部分的に
除去した後、MOCVD法によりInGaAs層7を選
択的にエピタキシャル成長する。続いて、5iO26を
表面にCVD法により形成し、ドライエツチングにより
側壁のみ残し、T i/ A Qを蒸着し、リフトオフ
法により、ソー12− スミ極8、ドレイン電極8′及びゲート電極9を形成す
る。
Example 4 Hereinafter, manufacturing of a semiconductor device of the present invention will be explained. FIG. 3 is a cross-sectional view of a field effect transistor. (10
0) Semi-insulating G tilted 5 degrees in the (011) direction from the plane
Undoped G is deposited on the aA s substrate 1 by MBE method.
aAs2 (500nm), undoped Ino, □Ga
o, As layers 3 (10 nm) are sequentially stacked. In the undoped I n, 1 Gao, As layer, I X 1
An SL delta doped layer 3' of 0 cm-2 is inserted.Furthermore, an undoped GaAs layer 4 is formed by MBE method.
(10 nm) and undoped AflGaAs layer 5 (20 nm)
(nm) are stacked. Subsequently, an undoped G a
After partially removing the s-layer 4 and the undoped AflGaAs layer 5, an InGaAs layer 7 is selectively epitaxially grown by MOCVD. Subsequently, 5iO26 is formed on the surface by the CVD method, only the side walls are left by dry etching, Ti/AQ is evaporated, and the saw 12, the drain electrode 8', and the gate electrode 9 are formed by the lift-off method. do.

上記方法により作製した電界効果トランジスタは、ゲー
ト長を0.15μmとした場合、K値13と、(100
)面の基板を用いた場合のに値7に比して著しい性能向
上が達成できた。
The field effect transistor manufactured by the above method has a K value of 13 and (100 μm) when the gate length is 0.15 μm.
) A significant performance improvement was achieved compared to the value of 7 when using a substrate with a surface of ).

また、この時、基板を5度オフしているため、表面平坦
性が良く、かつ、In組成の低下がなく再現性の良い性
能が得られた。
Furthermore, since the substrate was turned off 5 times at this time, good surface flatness was obtained, and performance with good reproducibility was obtained without a decrease in the In composition.

〔発明の効果〕〔Effect of the invention〕

本発明によれば、基板表面を低指数面から傾斜させた基
板上にエピタキシャル成長を行なうため以下に示す効果
を奏する。
According to the present invention, since epitaxial growth is performed on a substrate whose surface is inclined from a low index plane, the following effects are achieved.

1、表面平坦性に優れた結晶を得ることができた。1. A crystal with excellent surface flatness could be obtained.

2、エピタキシャル結晶構成原子の付着係数を増大する
ことができた。
2. The adhesion coefficient of atoms constituting the epitaxial crystal could be increased.

3、添加不純物原子の活性化率を向上することができた
。
3. The activation rate of added impurity atoms could be improved.

さらに、上記エピタキシャル成長法を用いて、高濃度不
純物層を有する高性能半導体装置を再現性良く作製する
ことができた。
Furthermore, using the epitaxial growth method described above, a high-performance semiconductor device having a highly-concentrated impurity layer could be manufactured with good reproducibility.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は、本発明のエピタキシャル成長法の第2の実施
例を説明するためのI nx G al−x A sの
In組成のオフ角度依存性を示す図、第2図は、本発明
のエピタキシャル成長法の第3の実施例を説明するため
のシートキャリア濃度のオフ角度依存性を示す図、第3
図は、本発明の一実施例の半導体装置の断面図である。 1・・・半絶縁性GaAs基板 2・・・アンドープG a A s 3・・・アンドープIn。、1Gao、、As層3′・
・・デルタドープ層 4・・・アンドープGaAs層 5・・・アンドープAQGaAs層 6−8in2      7− InGaAs層8・・
・ソース電極    8′・・・ドレイン電極9・・・
ゲート電極
FIG. 1 is a diagram showing the off-angle dependence of the In composition of Inx Gal-x As for explaining the second embodiment of the epitaxial growth method of the present invention, and FIG. Figure 3 shows off-angle dependence of sheet carrier concentration for explaining the third example of the method.
The figure is a sectional view of a semiconductor device according to an embodiment of the present invention. 1...Semi-insulating GaAs substrate 2...Undoped GaAs 3...Undoped In. , 1Gao, ,As layer 3'・
...Delta doped layer 4...Undoped GaAs layer 5...Undoped AQGaAs layer 6-8in2 7-InGaAs layer 8...
・Source electrode 8'...Drain electrode 9...
gate electrode

Claims (1)

【特許請求の範囲】 1、低指数面から所望の方向に傾けた表面面方位を有す
る化合物半導体単結晶基板を用い、該基板とは異なる構
成元素を有する薄膜結晶を成長させることを特徴とする
エピタキシャル成長法。 2、表面面方位を低指数面から傾けた化合物半導体単結
晶基板を用い、該基板表面に形成された原子ステップ列
に対しての付着係数が低指数面での付着係数に比して大
きい元素を少なくとも構成元素として含む化合物半導体
を成長させることを特徴とするエピタキシャル成長法。 3、低指数面から所望の方向に傾けた表面面方位を有す
るIII−V族化合物半導体単結晶基板上に少なくともI
nを構成元素として含む化合物半導体薄膜を成長させる
ことを特徴とするエピタキシャル成長法。 4、上記化合物半導体薄膜は、(In、Ga)Asであ
る請求項3記載のエピタキシャル成長法。 5、上記表面面方位は上記低指数面から2度以上傾いて
いることを特徴とする請求項1、2又は3記載のエピタ
キシャル成長法。 6、請求項1から5までのいずれかに記載のエピタキシ
ャル成長法により成長してなる化合物半導体薄膜を有す
ることを特徴とする半導体装置。 7、表面面方位を低指数面から傾けた化合物半導体単結
晶基板上に、該基板の構成元素とは異なる構成元素を有
するエピタキシャル成長層を設け、該エピタキシャル成
長層上に、半導体素子の少なくとも一部分が配置された
ことを特徴とする半導体装置。 8、表面面方位を低指数面から傾けた化合物半導体単結
晶基板上に、該基板の格子定数とは異なる格子定数を有
するエピタキシャル成長層を設け、該エピタキシャル成
長層上に、半導体素子の少なくとも一部分が配置された
ことを特徴とする半導体装置。 9、表面面方位を低指数面から傾けたIII−V族化合物
半導体単結晶基板上に、少なくともInを構成元素とし
て含むエピタキシャル成長層を設け、該エピタキシャル
成長層を不純物を有することを特徴とする半導体装置。 10、上記不純物は、上記エピタキシャル成長層の一原
子面に存在することを特徴とする請求項9記載の半導体
装置。 11、上記エピタキシャル成長層は、上記半導体素子の
能動層として配置されたことを特徴とする請求項7から
10のいずれかに記載の半導体装置。
[Claims] 1. A compound semiconductor single crystal substrate having a surface orientation tilted in a desired direction from a low index plane is used to grow a thin film crystal having constituent elements different from that of the substrate. Epitaxial growth method. 2. Using a compound semiconductor single crystal substrate whose surface orientation is tilted from a low-index plane, an element whose adhesion coefficient to the atomic step array formed on the substrate surface is larger than that on the low-index plane An epitaxial growth method characterized by growing a compound semiconductor containing at least as a constituent element. 3. At least I
An epitaxial growth method characterized by growing a compound semiconductor thin film containing n as a constituent element. 4. The epitaxial growth method according to claim 3, wherein the compound semiconductor thin film is (In, Ga) As. 5. The epitaxial growth method according to claim 1, 2 or 3, wherein the surface plane orientation is inclined by 2 degrees or more from the low index plane. 6. A semiconductor device comprising a compound semiconductor thin film grown by the epitaxial growth method according to any one of claims 1 to 5. 7. An epitaxial growth layer having a constituent element different from that of the substrate is provided on a compound semiconductor single crystal substrate whose surface orientation is inclined from a low index plane, and at least a portion of a semiconductor element is disposed on the epitaxial growth layer. A semiconductor device characterized by: 8. An epitaxial growth layer having a lattice constant different from that of the substrate is provided on a compound semiconductor single crystal substrate whose surface orientation is inclined from a low index plane, and at least a portion of a semiconductor element is disposed on the epitaxial growth layer. A semiconductor device characterized by: 9. A semiconductor device characterized in that an epitaxial growth layer containing at least In as a constituent element is provided on a III-V group compound semiconductor single crystal substrate whose surface orientation is tilted from a low index plane, and the epitaxial growth layer has impurities. . 10. The semiconductor device according to claim 9, wherein the impurity is present in one atomic plane of the epitaxial growth layer. 11. The semiconductor device according to claim 7, wherein the epitaxial growth layer is arranged as an active layer of the semiconductor element.
JP2176690A 1990-01-31 1990-01-31 Epitaxial growth method and semiconductor device Pending JPH03225928A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2176690A JPH03225928A (en) 1990-01-31 1990-01-31 Epitaxial growth method and semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2176690A JPH03225928A (en) 1990-01-31 1990-01-31 Epitaxial growth method and semiconductor device

Publications (1)

Publication Number Publication Date
JPH03225928A true JPH03225928A (en) 1991-10-04

Family

ID=12064196

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2176690A Pending JPH03225928A (en) 1990-01-31 1990-01-31 Epitaxial growth method and semiconductor device

Country Status (1)

Country Link
JP (1) JPH03225928A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0631299A4 (en) * 1993-01-13 1997-05-14 Sumitomo Chemical Co EPITACTIC SEMICONDUCTOR SUBSTRATE.

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0631299A4 (en) * 1993-01-13 1997-05-14 Sumitomo Chemical Co EPITACTIC SEMICONDUCTOR SUBSTRATE.

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