JPH0322637B2 - - Google Patents

Description

TECHNICAL FIELD The present invention relates to a display control circuit, and more particularly to a display control integrated circuit that integrates a CRT display and an LCD display control circuit into a single IC chip.

Prior Art Conventionally, CRT displays and LCD displays have been put into practical use as display devices. And usually the display is
Either a CRT display or an LCD display is used.
Therefore, two control circuits, a CRT display control circuit and an LCD display control circuit, are provided, and one of them can be selected and used. However, this requires the provision of two chips: an integrated circuit for CRT display control and an integrated circuit for LCD display control, resulting in disadvantages such as increased cost and increased power consumption.

Purpose of the invention In order to solve the above problems, the present invention has the following features:
The objective is to provide a display control integrated circuit that incorporates CRT display and LCD display control in a single chip.

Means for Solving Problems In the present invention, an LCD display control signal is obtained using the output of a CRT display control circuit.
Unlike CRTs, LCDs require unique timing, but when it comes to display operations, they share many operations with CRT displays. Therefore,
In the present invention, the output of the CRT display control is used as the input for the LCD display control, and a part of the output is shared, and this is integrated into one chip, thereby reducing the cost and power consumption of the device.

An example of the system configuration of the present invention is shown in FIG. The contents of display data memory 1 are stored in IC2 for display control.
The required display timing and display data are supplied to the CRT 3 to form a display screen, and the display on the LCD 4 is also enabled at the same time. As a display device, it is not necessary to use both at the same time; only one is normally used. Display control
IC2 has a CRT on one chip as shown in Figure 2.
It has a built-in display control circuit 5 and an LCD display control circuit 6. Then, as shown in Figure 3, the display control IC
There are two types of CRT display timing signals 7 and LCD display timing signals 8. The CRT display timing signal 7 requires HSYNC, which becomes the horizontal synchronization signal, VSYNC, which becomes the vertical synchronization signal, and DOT, which becomes the display data signal.For the LCD display timing signal 8, DOT, which becomes the display data, is shared, and other Frame signal FRM, common start signal DY,
A total of six signals are required: the latch pulse LP, the dot data timing SCK of the dot signal, and the display start timing BLNK.

FIG. 4 shows the display panel section of the LCD. The common side of the LCD panel 9 is equipped with a shift register 13 and an analog driver 14.
LP is input as the clock of 3, and the common start is
It is DY. In addition, the segment side is provided with a shift register 10, a latch 11, and an analog driver 12, and a timing signal SCK of dot data is provided.
DOT is written into the shift register 10, and the next latch pulse signal LP transfers the contents of the shift register 10 to the latch 11, which is displayed in the next display period. A frame signal FRM is input to the analog drivers 10 and 14 on the common side and the segment side, and the voltage applied to the LCD is converted to alternating current in one frame period.

These LCD display timing signals are generated by the LCD display control circuit of the display control IC. However, in view of speed, some of these signals may be configured by external circuits. The minimum required signals are common start signal DY, latch pulse LP, and data clock.
SCK, and display start signal BLNK. Also,
In the present invention, in the display control IC, data displayed on the LCD is created under the control of the display control IC during the immediately preceding raster scan period (that is, the immediately preceding display data output period).

Embodiment of the Invention An embodiment of the invention is shown in FIG. 5, which is comprised of six basic blocks 15-21, each having a required timing output. In the figure, DOT is the display data output, and 1
Data is output in bit serial or 4 to 8 parallel. Since this part is very high speed, the dot control circuit may be externally attached in some cases.
BLNK is a signal output indicating the display start position (display period). HSYNC is a horizontal synchronization signal and serves as a raster scan synchronization signal. VSYNC is a vertical synchronization signal, which is a display synchronization signal for one screen. On the other hand, on the LCD display control side in the figure, FRM is
This is an AC drive signal for display, and in LCD display, the voltage applied to the liquid crystal must be changed to AC in one or two frames, so it is used as an AC conversion timing signal. DY is a signal representing a common start signal and indicates the beginning of the LCD display screen. LP is a segment data latch signal, which is a timing signal for displaying segment data for each raster scan. SCK is a data clock and indicates the output timing of display data. In the configuration and operation of each part, the clock input (CLK) is the basic clock for each block 15 to 21 and is a synchronization signal for display data, but any number of clocks may be used for the display data. The horizontal synchronization control block 16 divides CLK and generates the horizontal synchronization signal HSYNC and display memory address, and the vertical synchronization control block 17
CLK and the output signal of horizontal synchronization control block 16 generate VSYNC and display memory address. A display start signal BLNK is generated in the display position control block 15 by the output signals of the horizontal synchronization control block 16 and the vertical synchronization control block 17. Then, from the output signal of the display position control block 15 and the display memory data, the dot data control block 21
Generates display data DOT. Here, the dot data control block 21 may be an external circuit for reasons such as speeding up. Further, the LCD display control circuit side B inputs each output signal of the display position control block 15, horizontal synchronization control block 16, and vertical synchronization control block 17 of the CRT display circuit side A, and the frame control block 18 outputs the frame control signal.
A common control block 19 generates a common control signal LP. Furthermore, the output of the display position control block is input, and the segment control block 20 generates the segment control signal SCK20.

FIG. 6 shows a waveform diagram of each display control signal. A display period occurs when BLNK goes from "L" to "H", and a period during which HSYNC goes "H" is a horizontal synchronization signal period, and the period including the preceding and following periods is suppressed by the BLNK signal so that it is not displayed. The waveforms shown in the fourth column and below are compressed as shown by the dashed line, and there is HSYNC in each section corresponding to BLNK, and HSYNC is gathered.
VSYNC becomes “H” and the screen becomes one screen. DOT is display data, and during the display period, dot data is generated as display data during a period when the BLNK signal is not input. Furthermore, in the case of LCD, FRM, DY,
LP signal is generated and LP is HSYNC as described above.
DY is a signal indicating the common start position and corresponds to VSYNC. In the figure, FRM has one period in the period of DY.

Although one embodiment has been shown above, the present invention is not limited to this and can be modified in many ways. For example, HSYNC and VSYNC have been explained as output signals, but the same effect can be achieved even if they are input from the outside. be. CLK is arbitrary for display data (integer multiple)
The clock is fine. Further, although the data to the display memory address is shown with terminals divided into input and output for explanation, the same applies to input and output in order to save terminals.

Effects of the Invention As detailed above, LCD displays require unique timing signals, but since the display has many operations common to CRT displays, the CRT display control circuit 5 and the liquid crystal display control circuit 6 can be integrated into one chip. The CRT display control circuit 5 includes a horizontal synchronization control block 16 that outputs a horizontal synchronization signal to a first external terminal, and a horizontal synchronization control block 16 that outputs a vertical synchronization signal to a second external terminal based on the horizontal synchronization signal. and a display position control block 15 that receives the horizontal synchronization signal and the vertical synchronization signal and outputs a display position signal indicating the start or end of the CRT display screen to a third external terminal. , the liquid crystal display control circuit 6 includes a segment control block that outputs a data pulse to a fourth external terminal during the display period of the display position signal, and a segment control block that outputs a data pulse to a fourth external terminal during the display period of the display position signal, and a segment control block that outputs a data pulse to a fourth external terminal during the display period of the display position signal, and a polarity control block that outputs a data pulse to a fourth external terminal in response to the beginning or end of the display period of the display position signal. a frame control block that outputs a frame signal to be inverted to a fifth external terminal, outputs a latch pulse in response to the horizontal synchronization signal to a sixth external terminal, and starts liquid crystal display from the display position signal and the vertical synchronization signal; According to the present invention, which is a display control integrated circuit characterized by comprising a common control block that outputs a common start signal indicating a common start signal to a seventh external terminal, a circuit for generating signals of different parts is added to a CRT display control circuit. By incorporating the display control circuit into a single chip, cost reduction, miniaturization, and lower power consumption can be expected.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an example of a system configuration in the display control integrated circuit of the present invention, FIG. 2 is a schematic diagram of the display control integrated circuit of the present invention, and FIG. 3 is each output signal of the display control integrated circuit of the present invention. Figure 4 shows
FIG. 5 is a block diagram of the display control integrated circuit of the present invention, and FIG. 6 is a waveform diagram of each signal in the display control integrated circuit of the present invention. Main symbols: 1...Display data memory, 2...Display control IC, 3...CRT, 4...LCD, 5...
CRT display control circuit, 6...LCD display control circuit,
7...CRT display timing signal, 8...LCD display timing signal.

Claims (1)

[Claims] 1. A CRT display control circuit 5 and a liquid crystal display control circuit 6 are included in one chip, and the CRT display control circuit 5 receives a horizontal synchronizing signal from a first
Horizontal synchronization control block 16 outputs to external terminal of
a vertical synchronization control block 17 that outputs a vertical synchronization signal to a second external terminal based on the horizontal synchronization signal; and a display indicating the start or end of a CRT display screen in response to the horizontal synchronization signal and the vertical synchronization signal. and a display position control block 15 that outputs a position signal to a third external terminal, and the liquid crystal display control circuit 6 has a segment control block that outputs a data pulse to a fourth external terminal during the display period of the display position signal. a frame control block that outputs a frame signal whose polarity is inverted to a fifth external terminal in response to the start or end of the display period of the display position signal; A display control integrated circuit comprising a common control block that outputs a common start signal indicating the start of liquid crystal display from the display position signal and the vertical synchronization signal to a seventh external terminal as well as outputs it to an external terminal. .