JPH0322710B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to Josephson integrated circuits, and more particularly to a wiring structure suitable for forming highly densely integrated circuits.

(Prior art and its problems) A typical switching operation of a circuit using a tunnel-type Josephson junction will be explained using a latch-type logic circuit as an example. In this type of logic circuit, the superconducting current flowing through the Josephson junction is switched by the gate current or the magnetic field created by the gate current, and the load R _L
Logic operations are performed by flowing into the flow. The switching time required for this operation is expressed as τ=C _J R _L + (L+L _G )/R _L (1). Here, C _J is the capacitance of the junction, L is the inductance of the wiring, and L _G is the inductance of the next stage gate. The first term is the rise time of the voltage across the junction, and the second term is the time required for current to flow to the gate of the next stage. C _J is where ε _O is the dielectric constant in vacuum, ε _* is the relative permittivity of the tunnel barrier layer, d is the thickness of the tunnel barrier layer, and S is the junction area, C _J = ε _O ε _* S/d... (2) where L is μ _O is the magnetic permittivity in air, l is the length of the wiring, W is the wiring width, t is the thickness of the interlayer insulator layer, and λ ₁ and λ ₂ are the first and second layers, respectively. The penetration depth of the magnetic field into the superconductor layer is L=μ _O l/W(t+λ ₁ +λ ₂ )...(3). L _G is determined to satisfy the relationship L _G φ _O /I (4), where I is Josephson current and φ _O is magnetic flux quantum. As circuits become denser and circuit components become smaller, the following phenomena occur. Since the junction area S decreases, the junction capacitance C _J decreases, but on the other hand, the wiring inductance L increases because the wiring width W decreases more than the wiring length l. As a result, it is difficult to significantly shorten the switching time in highly integrated circuits. In equation (3), the amount that can be changed relatively easily is the film thickness t of the interlayer insulating layer, and reduction of this t is essential for high-speed operation.

As a conventional example, the IBM J.Res.
Develop.) Vol. 2, No. 2, pp. 195-205. A cross-sectional structure of the wiring portion of this interferometer for logic circuits and memory circuits is shown in FIG. A first superconductor layer 52 serving as a ground plane is formed on the surface of a substrate 51, and a second superconductor layer 54 serving as wiring is placed on top of this via an insulating layer 53. The insulator layer 53 is a 25-35 mm niobium anodic oxide film (Nb ₂ O ₅ film) for the purpose of insulation between the first superconductor layer 52 and the second superconductor layer 54
and a 145-275mm silicon monoxide (SiO) film. Although not shown in FIG. 5, in the gate part, a thicker SiO film is formed between the first superconductor layer 52 and the second superconductor layer 52 in order to insulate the superconductor layer and resistor layer necessary for gate operation. is formed between the superconductor layer 54 and the superconductor layer 54. However, in order to reduce the inductance L of the wiring at wiring locations other than the gate part, a step is provided at the gate boundary part, and the insulating layer 5 between the first superconductor layer 52 and the second superconductor layer 54 is
The film thickness t of No. 3 is made as thin as possible. However, as densification progresses and each component of the circuit becomes smaller,
As the processing technology and lithography technology required for this process become more sophisticated, it is important to flatten the sample surface before these processes. As a result, the film thickness t of the insulator layer 53 increases, and the inductance L of the wiring increases, which impedes high-speed operation of logic and memory circuits.

(Objective of the Invention) The present invention aims to provide a Josephson integrated circuit wiring which eliminates such conventional drawbacks.

(Structure of the Invention) According to the present invention, in the Josephson integrated circuit wiring comprising a second superconductor layer formed on a first superconductor layer via a spacer layer, the spacer layer includes at least A wire for a Josephson integrated circuit is obtained, which is characterized by being made of an insulator composite film including a third superconductor layer directly below the second superconductor layer with a thin insulating layer interposed therebetween.

(Detailed description of the structure) According to the invention, the thickness of the insulating layer between the second superconductor layer serving as the wiring and the third superconductor layer below it is equal to the thickness of the entire spacer layer. Regardless of film thickness,
Since the wiring can be selected to be thin enough to reduce inductance, high-speed operation can be maintained even when the circuit density increases.

(Example) Hereinafter, the present invention will be described in detail using the drawings.

FIG. 1 is a drawing showing an embodiment of the present invention. In the figure, a first superconductor layer 12 is formed on the surface of a substrate 11, and a third superconductor layer 13 and a first insulator layer 14, which partially extend thereon, are on the same plane. A third insulating layer 15 is formed on the second insulating layer 15 provided on the second insulating layer 15.
A second superconducting electrode 16 serving as a wiring is arranged above the superconducting electrode layer 13 . In this structure, the thickness t of the interlayer insulator layer in equation (3), which represents the inductance of the wiring, is determined only by the second insulator layer 15, and this thickness is the same as that of the first and second insulator layers 15.
Independently of the film thickness of the spacer layer consisting of 4 and 15, it can be made sufficiently thin within a range that maintains electrical insulation between the second and third superconductor layers 16 and 13. Therefore, even if the thickness of the first insulating layer 14 increases due to the planarization of each constituent layer of the element due to higher circuit density, the increase in wiring inductance L can be suppressed.

Further, as another embodiment, there is a structure as shown in FIG. In this figure, the numbers representing each component are used in common with those in FIG. The structure of FIG. 2 has the following features, except that the second insulator layer 15 is formed only on top of the third superconductor layer 13.
This is the same as in FIG. In this structure, in addition to the effects obtained with the structure shown in FIG.
Since an insulating layer film such as an anodic oxide film formed from the third superconductor layer 13 itself can be used as the third superconductor layer 13, a thin and dense film with few pinholes can be obtained.

Still another example is the structure shown in FIG. In this figure as well, the numbers indicating each component are used in common with those in FIGS. 1 and 2. In the structure of FIG. 3, the second insulator layer shown in FIGS. 2 and 1 is interposed between the second and third superconductor layers 16 and 13, respectively. They are arranged in a two-layer configuration as layers 15 and 15'. In addition to the inductance of the wiring, impedance matching between the wiring and the load is important for high-speed operation of the device. By making an appropriate selection, both conditions can be satisfied.

Next, a method of manufacturing the Josephson integrated circuit wiring shown in the above embodiment will be explained with reference to FIG.

First, a first superconductor layer 42 made of niobium (Nb) or the like is formed on a substrate 41. This first superconductor layer 42 generally functions as a ground plane. Although not shown in FIG. 4a, since a gate portion including a Josephson junction is formed on the first superconductor layer 42 via an insulating layer, the superconductor layer necessary for this is formed. A first insulator layer 43 consisting of an insulator layer between resistor layers and an insulator layer for planarization is formed (FIG. 4a). On top of this, an etching mask 44 is formed using normal lithography technology, and the underlying first superconductor layer 43 is processed by anisotropic etching such as reactive sputter etching (FIG. 4b). .
Next, after sputter cleaning the exposed surface of the first superconductor layer 42, a third superconductor layer 45 made of Nb or the like is deposited using a film forming method with excellent directionality such as vapor deposition. Continue to lift off (Figure 4c). After the sample surface is coated with a second insulator layer 46 such as silicon monoxide (SiO) or silicon dioxide (SiO ₂ ), a second superconductor layer 45 is coated on top of the third superconductor layer 45 to serve as wiring. Form layer 47. This second
The patterning of the superconductor layer 47 is performed by an etching method or a lift-off method using ordinary lithography techniques (FIG. 4d).

Another method for forming wiring is to perform anodization or plasma oxidation on the surface of the third superconductor layer 45 after the configuration shown in FIG.
There is a method in which a second insulator layer 46 is formed only on the top, and a second superconductor layer 47 serving as wiring is formed thereon (FIG. 4e). In addition, as another method, the fourth
After the step in FIG. 4c, a second insulator layer 46 is formed on the surface of the third superconductor layer 45 in the same manner as in FIG. After forming the insulator layer 46', a superconductor layer 4 is formed thereon.
7 (Fig. 4f).

In the above embodiment, the case where the third superconductor layer is in contact with the first superconductor layer is explained, but the third superconductor layer is in contact with the first superconductor layer through the insulator layer. This also includes cases where the body layer and the insulating layer are formed.

(Effects of the Invention) As explained above, according to the present invention, the thickness of the insulating layer under the wiring can be selected to be sufficiently thin regardless of the thickness of all the spacer layers, so that it is possible to increase the density of the circuit. Even if each constituent layer is planarized, the inductance of the wiring can be kept small. Note that the spread width of the third superconductor layer and the selection of the superconductor layer material and the insulator layer material, which were exemplified in the description of the above embodiments, do not limit the present invention in any way.

[Brief explanation of drawings]

1, 2, and 3 are cross-sectional views showing the first, second, and third embodiments of Josephson integrated circuit wiring according to the present invention, respectively, and FIGS. FIG. 5 is a sectional view showing a wiring structure used in a conventional Josephson integrated circuit. In the figure, 11, 41, 51 are substrates, 12,
42, 52 are first superconductor layers, 13, 45 are third superconductor layers, 14, 43, 53 are first insulator layers or insulator layers, 15, 46 are second insulators. layers 15', 46' are third insulator layers 16, 4;
7 and 54 are second superconductor layers, and 44 is an etching mask.

Claims (1)

[Claims] 1. A wiring for a Josephson integrated circuit consisting of a second superconductor layer formed on a first superconductor layer with a spacer layer in between, wherein the spacer layer is at least immediately below the second superconductor layer. Wiring for a Josephson integrated circuit characterized by comprising an insulator composite film including a third superconductor layer through a thin insulator layer.