JPH0322728A - Buffer check in duplexing system circuit - Google Patents

Abstract

PURPOSE:To output normal data at all times without requiring a long time to decide a fault place by making a buffer check on an output side. CONSTITUTION:Switching control is preformed by switching control circuits 13 and 23 so that, for example, the buffer output of a 0 system is led out as output data when comparing means 18 and 28 decide that the outputs of 0- system and 1-system pattern generating means 17 and 27 coincide with pattern outputs obtained by inserting the outputs into dummy time slots and passing them through 0-system and 1-system buffers 12 and 22 or the buffer output of an 1-system is led out as the output data. Therefore, the faults of output-side buffers 12 and 22 are also detected and normal data is outputted. Consequently, data processing of high quality is performed speedily without requiring a long time for the error processing.

Description

[Detailed Description of the Invention] [Summary] Regarding the method of checking the output buffer when the outputs of each duplexed circuit are combined via a buffer and the output of one of the buffers is taken out, the output side of the duplex system is checked. The purpose is to provide a redundant system circuit that can detect failures in the O-system/I-system buffers. If the pattern output of the 0-system/l-system pattern generating means via the 0-system/l-system pattern generating means matches, the buffer output of the 0-system is taken out as output data, and if the comparison result by the comparing means does not match, switching is performed by the mismatch signal from the comparing means. access the control circuit,
The configuration is such that a switching control circuit performs switching control so that the buffer output of the first system is taken out as output data.

[Industrial application field]

The present invention relates to a method for checking an output buffer when the outputs of duplicated circuits are combined via a buffer and the output of one of the buffers is taken out.

In order to combine the output sides of duplicated circuits in order to increase reliability, processing is often performed to combine them via a buffer and take out the output of one of the buffers.

[Conventional technology]

FIG. 4 is a diagram illustrating a conventional example of a duplex system circuit, and FIG. 5 is a diagram illustrating a time chart in the conventional duplex system circuit.

Figure 4 shows a circuit in which the data processing system for digital data synchronization detection, phase alignment, and alarm detection processing is duplicated (
b), (C) and its duplicated circuit (b),
The structure of (C) or the same structure, or the data processing circuit 11 that performs synchronization detection, phase alignment, and alarm detection.
．． 21, a buffer 12.22 for taking out the output of the data processing circuit 11.21, and a buffer 12.22 for taking out the output of the data processing circuit 11.21, and a buffer 12.22 for transferring the output from one system to the other system when an abnormality is detected in data synchronization detection or phase matching in the data processing circuit 11.21. A switching control circuit 13.23 is provided to control switching to.

In addition, the dual system circuit (b). (C) Buffers 12 and 2
The output sides of the two are coupled to form a coupling part (a), and the output of one of the buffers is taken out.

The time chart in FIG. 5 shows the flow of data in the duplicated data processing system shown in FIG. 4, and is a time chart until the input digital data is processed as described above and taken out.

Figure 4 below. The operation will be explained using FIG.

That is, input digital data is conveyed using time slots (hereinafter referred to as TS) as shown in FIG. 5(1).

Figure 5 (1) is carried using TSI, TS2, and TS3, with gummy TSI and dummy TS2 between TSI and TS2.
This is the case where it is assumed that is inserted.

The digital data input in this state is sent to each of the duplicated data processing circuits 1l. 2l performs synchronization detection, phase alignment, and alarm detection as shown in Figure 5 (2). (
As shown in 3), the signal is sent to the buffer 12.22 of each system, and taken out via the coupling part (a) forming the output side of the buffer 12.22 of the 0 system or I system.

As mentioned above, in the duplex system circuits (b) and (C), the same data is processed at the same timing in both systems up to the input side of the buffer 12.22, and the buffer 1 of one system is
Data processed by activating 2.22. Take out.

FIG. 5(4) shows an example when an abnormality is detected in the data processing circuit 1l or 21 as described above and the buffers 12 and 22 are switched to active through the switching control circuits 13 and 23, and TS1 is set to 0. The system or 1 system buffer 12.22 is activated, and if an abnormality as described above is detected in the data processing circuit 11.21 of the activated system,
In response to a signal from the data processing circuit 11.21, the switching control circuit 13 or 23 makes its own buffer 12.22 inactive, activates the other buffer 22 or 12 via the other switching control circuit 23 or 13, The data processed through the buffer 22 or l2 on the active side is taken out through the coupling part (a).

FIG. 5 (5) shows a situation in which digital data is taken out via the buffer 12.22, and in the same state as in FIG.
They are taken out in the order of S3.

[Problem to be solved by the invention]

In the case of the conventional example shown in Fig. 4, an abnormality in the duplexed buffer 12.22 is normally not detected, and even if a failure such as an operational abnormality occurs in the buffer 12.22 in the active state, the other buffer is not detected. System switching is not performed, and the data is directly retrieved via the faulty buffer 12.22.

Therefore, the redundant system circuit (c). An error occurs in, for example, a data conversion circuit (not shown) that receives the output of (C),
It will take a lot of time to process the error.

However, as higher quality data processing is required to be performed more quickly, a duplex system with higher reliability becomes necessary.

SUMMARY OF THE INVENTION An object of the present invention is to provide a duplex system circuit that can also detect failures in buffers forming the output side of the duplex system.

[Means to solve the problem]

FIG. 1 is a diagram illustrating the principle of buffer checking in a duplex circuit according to the present invention.

The duplication system circuits (c) and (c) of the present invention include a switching control circuit 13.23 that performs the same operation as explained in FIG.
It comprises a 0 series/1 series pattern insertion means 14.24, an O series/1 series pattern generation means 17.27, and a comparison means 18.28, and the above-mentioned 0 series/1 series pattern insertion means 14.24 , a certain determined data pattern is inserted into the dummy time slot, and the 0 system/1 system pattern generation means 17.27 generates data to be inserted into the dummy time slot by the O system/1 system pattern insertion means 14.24. The comparison means 18.28 is the O system/1 system pattern generation means 1.
7.27 output and 0 system/1 system pattern insertion means 14.2
4 is compared with the output via the 0-system/1-system buffer 12.24, and if the comparison result by the comparison means 18.28 does not match, the switching control circuit 1 is sent by a mismatch signal.
3.23, the switching control circuit 13.23 controls the buffer output of the act system to be stopped and the buffer output of the non-act system to be taken out as output data, and the buffer is checked in this way and the buffer is checked for act. This is a means to solve this problem by switching and controlling the system.

[For production]

Comparison means 18.0 system/1 system pattern generation means 17 at 28
．． If the output of 27 and the pattern output inserted into the dummy time slot and passed through the O system/l system buffer 12.24 match, for example, take out the 0 system buffer output as output data, and if they do not match, is the switching control circuit 1 so as to take out the buffer output of the 1st system as output data.
By performing switching control at 3 and 23, it becomes possible to detect failures in the output side buffers 12 and 24 and output data without abnormalities.

〔Example〕

The gist of the present invention is shown in Figure 2 below. This will be explained in detail with reference to the embodiment shown in FIG.

FIG. 2 is a diagram illustrating an embodiment of the buffer check of the duplex circuit according to the present invention, and FIG. 3 is a diagram illustrating a time chart when checking the buffer of the duplex circuit according to the present invention.

Note that the same reference numerals indicate the same objects throughout the figures.

O system/1 system redundant system circuit of the present invention shown in Fig. 2 (c)
, (c) are pattern insertion circuits 14a, 24a as the O system/1 system pattern insertion means 14.24 explained in FIG.
, O-system/1-system pattern generation means IT, 27 as pattern generation sections 17a, 27a consisting of pulse generators (hereinafter referred to as PG) 15a, 25a and pattern generation circuits 16a, 26a, comparison means 18.28 as comparison means. Circuit 18a. This is an example constructed from 28a.

Note that the above-mentioned symbols 14a to 18a constitute O-system circuits, and symbols 24a to 28a constitute 1-system circuits, which perform the same operations.

Moreover, the above-mentioned O system/1 system circuit (b). (C) also includes data processing circuits 11 and 21, buffers 12 and 22, and a switching control circuit 13, which perform operations similar to those described in FIG.
It is equipped with 23.

Furthermore, the input side and the output side of the duplex system circuits (c) and (c) are combined, and the same data is simultaneously input and processed, and the duplex system circuit (c) and (c) are connected to the double-combined output side (this Data is output from one of the buffers 12 or 22 from the double coupling section (referred to as (a)).

The pattern generation circuits 16a and 26a of this embodiment are PG15.
A predetermined O/1 alternating data pattern is generated based on the pulses generated from a and 25a, and is inserted into the gummy TS via pattern insertion circuits 14a and 24a.

FIG. 3 shows a time chart when performing the above processing,
Insert the data pattern (indicated by pattern! in FIG. 3) from the O-system pattern generation unit 17a into the Gummy TSI,
An example will be shown in which a data pattern (indicated by pattern 2 in FIG. 3) from the pattern generating section 27a of the 1st system is inserted into the dummy TS2.

Therefore, if data is currently being output from the 0-series buffer 12 via the double coupling part (a) on the output side, then Gummy T
A comparison circuit 18 inserts an O/1 alternating data pattern into the SI, and compares what was inserted into the gummy TSI with the 0/1 alternating data pattern taken out to the output side of the buffer 12.
a, and if they match, it is assumed that there is no failure in buffer 12, and the data from buffer l2 is transferred to the double bond part (
Output via a).

If the comparison results in the comparison circuit 18a do not match, it is assumed that there is some kind of failure in the buffer 12, and the comparison circuit 18a stops outputting data from the buffer 12 via the switching control circuit 13. At 1
The switching control circuit 23 of the system is accessed and switching control is performed so that the data output from the buffer 22 is outputted via the double coupling part (a).

Now, from the buffer 22 of system 1 to the output side double coupling part (
If a failure in the buffer 22 is detected while outputting data via a), use the same process as above to make the O system buffer 12 the active system, and connect the buffer 12 to the output side double coupling section. Switching control is performed to output data via (a).

With the above-mentioned structure and processing, redundant system circuit (b), (c
) is also detected, so it is possible to always output normal data through the double coupling part (a). [Effects of the Invention] According to the present invention as described above, since a buffer check is performed on the output side, it does not take a long time to determine the location of a failure.
It is possible to provide a redundant circuit that always outputs normal data.

[Brief explanation of drawings]

FIG. 1 is a diagram explaining the principle of buffer checking of a duplex system circuit according to the present invention. FIG. 2 is a diagram explaining an embodiment of buffer check of a duplex system circuit according to the present invention. FIG. FIG. 4 is a diagram illustrating a conventional example of a duplex circuit; FIG. 5 is a diagram illustrating a time chart of a conventional duplex circuit. In the figure, 11.21 is a data processing circuit, 12.22 is a buffer, 13.23 is a switching control circuit, 14.24 is O system/1 system pattern insertion means, 14a, 2
4a is a pattern insertion circuit, 15a, 25a are PCs, 16a, 26a are pattern generation circuits, 17.27 is 0 system/1 system pattern generation means, 17a, 2
Reference numeral 7a indicates a pattern generation section, 18.28 a comparison means, and 18a and 28a a comparison circuit. FIG. 1 is a diagram illustrating the principle of buffer checking of a duplex circuit in the present invention.

Claims (1)

[Scope of Claims] A duplex system circuit in which a data processing system that performs synchronization detection, alarm detection, and phase alignment of digital data input in a plurality of time slots is duplicated, and the processed data is extracted from one of the systems. , a 0-series/1-series pattern insertion means (14
, 24); 0-system/1-system pattern generation means (17, 27) for generating the data pattern to be inserted into the dummy time slot by the 0-system/1-system pattern insertion means (14, 24); 0 system/1 system buffers (12, 22) that temporarily hold the outputs of the system/1 system pattern generation means (17, 27) and the outputs of the 0 system/1 system pattern insertion means (14, 24);
) is provided with comparison means (18, 28) for comparing the insertion pattern output when sent to the coupling part ((a)) forming the output side of the redundant system circuit ((b), (c)). , the comparing means (18, 28) inserts the output of the 0 system/1 system pattern generating means (17, 27) into the dummy time slot, and outputs the 0 system/1 system buffer (12, 22).
) via the 0 system/1 system pattern generation means (17, 2
7), the buffer output of the 0 system is taken out as output data, and if the comparison result from the comparison means (18, 28) does not match, the data from the comparison means (18, 28) is extracted. A duplex system circuit characterized in that the switching control circuit (13, 23) is accessed by a mismatch signal and the switching control circuit (13, 23) performs switching control so as to take out the buffer output of the first system as output data. Buffer check.