JPH0322732A - Fast clock recovering device - Google Patents

Abstract

PURPOSE:To decrease the number of times of correction when a phase difference is large and to enable fast clock recovery by increasing correction width at the time of a reception startup. CONSTITUTION:A reception startup detection part 5 and a correction frequency counter 8 are provided. Then the reception startup detectio part 5 detects the reception startup and the correction frequency counter 8 counts the number of times of phase correction from the reception startup and decreases the phase correction width gradually with the counted value to attain to a constant phase difference speedily. Consequently, when the phase difference is large at the time of the reception startup, a clock signal synchronized with a zero-cross signal can be regenerated in high speed.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a clock regeneration device used for data communications and the like.

Conventional technology FIG. 2 shows the configuration of a conventional clock regeneration device.

In FIG. 2, 1 is a zero cross signal input terminal,
It is connected to the zero cross detection section 6. 7 is an amplifier down counter 7, into which the output of the zero cross detection section is input together with the output of the fixed frequency divider 11. Reference numeral 9 denotes a correction width switching section, which switches the number of divisions of the variable frequency divider 10 in response to an input from the correction width setting terminal 4. 12 is a reference clock.

Next, the operation of the above conventional example will be explained. In FIG. 2, the up-down counter 7 calculates the direction of the phase difference between the zero-cross signal input and the fixed frequency divider 11 every time the zero-cross signal is input. When the frequency reaches a certain value, the frequency division number of the variable frequency divider 10 is switched. This allows the phase of the output signal of the fixed frequency divider 11 to match the zero-cross signal input.

In this way, the conventional clock reproduction device described above can also reproduce a clock synchronized with a zero-crossing signal.

Problems to be Solved by the Invention However, in the conventional clock regeneration device described above, since the frequency division value of the variable frequency divider 10 is switched by detecting a frame synchronization signal, etc., if there is a large phase difference at the rising edge of reception, There was a problem that the clock could not be regenerated at high speed.

The present invention solves these conventional problems,
The object of the present invention is to provide an excellent clock regeneration device that can regenerate clocks at high speed.

Means for Solving the Problems In order to achieve the above object, the present invention is provided with a reception rise detection section and a correction number counter.

Therefore, according to the present invention, the reception rise detection section detects the reception rise, the correction number counter counts the number of phase corrections from the reception rise, and the phase correction width is sequentially decreased according to the counted number. By doing this, it is possible to rapidly pull in the phase difference to a certain level.

Embodiment FIG. 1 shows the structure of an embodiment of the present invention. In FIG. 1, 2 is an unlock signal input terminal, and 3 is a press signal input terminal, which are input to the reception rise detection section 5. A correction number counter 8 is connected between the up/down counter 7 and the correction width switching section 9, and is also connected to the output of the reception rise detection section 5.

Next, the operation of the above embodiment will be explained. In the above embodiment, depending on the input state from the unrotation signal input terminal 2 and the press signal input terminal 3, the reception rise detection section 5 detects the rise of reception such as when the power is turned on, after transmission, after frequency switching, etc., and the correction frequency counter is detected. Reset.

The zero cross detector 6 detects the zero cross of the input signal of the zero cross signal input terminal 1 and generates a pulse, and the up/down counter 7 compares the direction of the phase difference with the output of the fixed frequency divider 11 to determine the phase shift. Count the number of times. When the number of times reaches a certain value, a signal is output to switch the division value of the variable frequency divider 10. A correction number counter 8 counts the number of times the signal is output. The correction width switching section 9 switches the frequency division value of the variable frequency divider according to the count number. By switching the division value of the variable frequency divider 10 so that the one-time correction width becomes smaller as the count number of the correction number counter increases, even if the phase difference is large at the start of reception, the correction can be performed at high speed. A clock that is synchronized with the zero-crossing signal can be regenerated.

Effects of the Invention As is clear from the embodiments, according to the present invention, the correction width can be increased at the rise of reception, and when the phase difference is large, the number of corrections can be reduced, and clock recovery can be performed at high speed. Moreover, by successively decreasing the correction width, there is an advantage that stable clock reproduction can be performed during normal operation.

[Brief explanation of the drawing]

FIG. 1 is a schematic block diagram of a clock regeneration device according to an embodiment of the present invention, and FIG. 2 is a schematic block diagram of a conventional clock regeneration device. 1...Zero cross signal input terminal, 2...Unlock signal input terminal, 3...Press signal input terminal, 4...
Correction width setting terminal, 5... Reception rise detection section, 6.
...Zero cross detection section, 7. Asogdown counter, 8. Correction number counter/ta, 9. Correction width switching section,
10...Variable division period, l1...Fixed division period, 12.
...Standard Kronk.

Claims (1)

[Claims] A rising detection section that detects the rising edge of reception, an up/down counter that counts the phase difference between the zero-crossing signal input and the internal clock, a correction number counter that counts the number of phase corrections from the rising edge of reception, and a frequency division value depending on the number of corrections. A clock regeneration device equipped with a variable frequency divider that switches between