JPH0322732B2 - - Google Patents
Info
- Publication number
- JPH0322732B2 JPH0322732B2 JP58128423A JP12842383A JPH0322732B2 JP H0322732 B2 JPH0322732 B2 JP H0322732B2 JP 58128423 A JP58128423 A JP 58128423A JP 12842383 A JP12842383 A JP 12842383A JP H0322732 B2 JPH0322732 B2 JP H0322732B2
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- JP
- Japan
- Prior art keywords
- mos transistor
- power supply
- amplifier
- terminal
- resistor
- Prior art date
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- 239000003990 capacitor Substances 0.000 claims description 16
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 claims description 6
- 238000007599 discharging Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 239000008188 pellet Substances 0.000 description 1
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Description
【発明の詳細な説明】
本発明は振幅制御信号発生回路に関し、特に電
流出力回路に振幅制御信号を供給する振幅制御信
号発生回路に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an amplitude control signal generation circuit, and more particularly to an amplitude control signal generation circuit that supplies an amplitude control signal to a current output circuit.
従来の振幅制御信号発生回路は、第１図に示す
ように、ゲート電極１にスイツチ信号を入力する
ＮチヤネルMOSトランジスタQ1のドレイン電流
で充電するコンデンサ７を有する充放電回路３１
に対応して、その出力信号端子９と第１電源端子
８間の振幅制御信号VCを電流出力回路３２のＰ
チヤネル電流出力用MOSトランジスタQ3（以下
Q3と略す）のゲート・ソース間に供給してQ3の
ドレイン電流である出力電流端子１３の出力電流
を制御している。 The conventional amplitude control signal generation circuit, as shown in FIG .
Correspondingly, the amplitude control signal V C between the output signal terminal 9 and the first power supply terminal 8 is outputted to P of the current output circuit 32.
Channel current output MOS transistor Q 3 (below
The output current of the output current terminal 13, which is the drain current of Q 3 , is controlled by supplying it between the gate and source of Q 3 (abbreviated as Q 3 ).
充放電回路３１は、MOSトランジスタQ1のド
レイン電極２と、抵抗５を接続し、該抵抗５の他
端子にコンデンサ７を接続し、該コンデンサ７の
他端子を第１電源端子８に接続し、前記MOSト
ランジスタQ1（以下Q1と略す）のソース電極３を
第２電源端子１７に接続している。 The charging/discharging circuit 31 connects the drain electrode 2 of the MOS transistor Q 1 to a resistor 5 , connects the other terminal of the resistor 5 to a capacitor 7 , and connects the other terminal of the capacitor 7 to the first power supply terminal 8 . , the source electrode 3 of the MOS transistor Q 1 (hereinafter abbreviated as Q 1 ) is connected to the second power supply terminal 17 .
このような回路ではQ1はスイツチング素子と
して動作し、Q1のゲート電極１に第１電源電位
を与える事によりQ1はオンし、コンデンサ７は
抵抗５とQ1を通して充電される。 In such a circuit, Q1 operates as a switching element, and by applying the first power supply potential to the gate electrode 1 of Q1 , Q1 is turned on, and the capacitor 7 is charged through the resistor 5 and Q1 .
今振幅制御信号として出力信号端子９からコン
デンサ７の端子電圧を振幅制御信号VCとして取
り出す時、その最大値は、第２電源端子１７が接
続されているので第１電源端子８との電圧で与え
られる。この振幅制御信号VCを電流出力回路３
２のQ3のゲート電極１０に供給しているので、
出力電流端子１３の出力電流値はQ3のしきい値
電圧VTとβに下記のように依存する。 Now, when the terminal voltage of the capacitor 7 is taken out from the output signal terminal 9 as an amplitude control signal V C , its maximum value is equal to the voltage with the first power supply terminal 8 since the second power supply terminal 17 is connected. Given. This amplitude control signal V C is applied to the current output circuit 3.
Since Q2 is supplied to the gate electrode 10 of Q3 ,
The output current value of the output current terminal 13 depends on the threshold voltage V T and β of Q 3 as follows.
IDQ3＝βQ3／２（VGSQ3−VTQ3）2
ここに、IDQ3：出力電流値
βQ3：Q3のβ
VGSQ3：Q3のゲート，ソース間電圧
VTQ3：Q3のVT
上式より、出力電流は、Q3のVTやβのばらつ
きや温度の影響を直接受けてて、VTやβのばら
つきや温度特性を持つてしまう事が明らかであ
る。 I DQ3 = βQ 3 /2 (V GSQ3 − V TQ3 ) 2where , I DQ3 : Output current value β Q3 : β of Q 3 V GSQ3 : Voltage between gate and source of Q 3 V TQ3 : V T of Q 3 From the above equation, it is clear that the output current is directly affected by the variations in V T and β of Q3 and the temperature, and has the variations in V T and β and temperature characteristics.
本発明は、従来のもののこのような欠点を除去
し、電流出力回路に用いた時、出力MOSトラン
ジスタのしきい値電圧VTやβのばらつき、温度
特性による出力電流のばらつきを除去しようとす
るものである。 The present invention attempts to eliminate these drawbacks of the conventional ones, and when used in a current output circuit, eliminates variations in the threshold voltage V T and β of the output MOS transistor, as well as variations in output current due to temperature characteristics. It is something.
本発明の振幅制御信号発生回路は第１電源に放
電抵抗と並列接続されているコンデンサの一端を
接続し、該コンデンサの他端と第１導電型MOS
トランジスタのドレイン電極とを充電抵抗を介し
て接続し、前記第１導電型MOSトランジスタの
ソース電極とバツクゲートとの接続点を増幅器の
出力端子に接続し、第２導電型MOSトランジス
タのソース電極及びバツクゲートを前記第１電源
に接続し、前記第２導電型MOSトランジスタの
ゲート電極を前記増幅器の出力端子に接続し、前
記第２導電型MOSトランジスタのドレイン電極
に前記増幅器の正相入力端子と抵抗の一端を接続
し、該抵抗の他端を第２電源に接続し、前記増幅
器の逆相入力端子を前記第２電源に対して基準電
圧を有する第３電源に接続し、ソース電極を前記
第１電源に接続する第２導電型の電流出力用
MOSトランジスタのゲート電極に前記コンデン
サの他端を接続して振幅制御信号を供給し、前記
第１導電型MOSトランジスタのゲート電極にス
イツチ信号を入力してスイツチ動作させて前記電
流出力用MOSトランジスタのドレイン電流を制
御して構成される。 The amplitude control signal generation circuit of the present invention connects one end of a capacitor connected in parallel with a discharge resistor to a first power supply, and connects the other end of the capacitor to a first conductivity type MOS
The drain electrode of the transistor is connected via a charging resistor, the connection point between the source electrode and the back gate of the first conductive type MOS transistor is connected to the output terminal of the amplifier, and the source electrode and the back gate of the second conductive type MOS transistor are connected to each other. is connected to the first power supply, the gate electrode of the second conductivity type MOS transistor is connected to the output terminal of the amplifier, and the drain electrode of the second conductivity type MOS transistor is connected to the positive phase input terminal of the amplifier and a resistor. one end of the resistor is connected to the second power source, the other end of the resistor is connected to a second power source, an anti-phase input terminal of the amplifier is connected to a third power source having a reference voltage with respect to the second power source, and a source electrode is connected to the first power source. For current output of the second conductivity type connected to the power supply
The other end of the capacitor is connected to the gate electrode of the MOS transistor to supply an amplitude control signal, and a switch signal is input to the gate electrode of the first conductivity type MOS transistor to operate the switch, thereby controlling the current output MOS transistor. It is configured by controlling the drain current.
以下本発明の実施例を図面について説明する。 Embodiments of the present invention will be described below with reference to the drawings.
第２図は本発明の一実施例の回路図で、１〜１
３およびQ1，Q3は従来例の第１図の充放電回路
３１と電流出力回路３２の同一部分を示す。電源
回路３０はＰチヤネルMOSトランジスタQ2（以
下Q2と略す）を有する。 FIG. 2 is a circuit diagram of one embodiment of the present invention.
3, Q 1 and Q 3 indicate the same parts of the charging/discharging circuit 31 and the current output circuit 32 of FIG. 1 of the conventional example. The power supply circuit 30 includes a P-channel MOS transistor Q 2 (hereinafter abbreviated as Q 2 ).
電源回路３０において、１４は増幅器２０の正
相入力端子、１５は増幅器２０の逆相入力端子、
１６は増幅器２０の出力端子、１７は第２電源、
１８は第３電源、１９は第２の抵抗R2、２０は
増幅器、２１はQ2のゲート電極、２２はQ2のソ
ース電極、２３はQ2のドレイン電極、２４はQ2
のバツクゲート、である。 In the power supply circuit 30, 14 is a positive phase input terminal of the amplifier 20, 15 is a negative phase input terminal of the amplifier 20,
16 is the output terminal of the amplifier 20, 17 is the second power supply,
18 is the third power supply, 19 is the second resistor R 2 , 20 is the amplifier, 21 is the gate electrode of Q 2 , 22 is the source electrode of Q 2 , 23 is the drain electrode of Q 2 , 24 is the Q 2
This is the back gate.
そして第１電源端子８にコンデンサ７の１端を
接続し、コンデンサ７の他端子とQ1のドレイン
電極２とを抵抗５を介して接続し、Q1のソース
電極３とバツゲート４との接続点S1を増幅器２
０の出力端子に接続し、Q2のソース電極２２及
びバツクゲート２４を第１電源端子８に接続し、
Q2のゲート電極２１を、増幅器２０の出力端子
に接続し、Q2のドレイン電極２３に増幅器２０
の正相入力端子と抵抗１９を接続し、抵抗１９の
他端子を第２電源端子１７に接続して接地し、増
幅器２０の逆相入力端子を第３電源端子１８に接
続する。 Then, one end of the capacitor 7 is connected to the first power supply terminal 8, the other terminal of the capacitor 7 is connected to the drain electrode 2 of Q 1 via the resistor 5, and the source electrode 3 of Q 1 is connected to the gate 4. Point S1 to amplifier 2
0, the source electrode 22 and back gate 24 of Q 2 are connected to the first power supply terminal 8,
The gate electrode 21 of Q 2 is connected to the output terminal of the amplifier 20, and the drain electrode 23 of Q 2 is connected to the output terminal of the amplifier 20.
The positive phase input terminal of the amplifier 20 is connected to the resistor 19, the other terminal of the resistor 19 is connected to the second power supply terminal 17 and grounded, and the negative phase input terminal of the amplifier 20 is connected to the third power supply terminal 18.
第２図において、Q1はスイツチング素子とし
て動作し、Q1のゲート電極１に第１電源電位を
与える事により、Q1はオンし、コンデンサ７は
抵抗５，Q1，増幅器２０を通して充電される。
このときコンデンサ７の充電収束電圧Vcmaxは、
第１電源電位と電源回路３０の増幅器１の出力電
位の電位差V1になる事は明らかである。 In FIG. 2, Q 1 operates as a switching element, and by applying the first power supply potential to the gate electrode 1 of Q 1 , Q 1 is turned on, and the capacitor 7 is charged through the resistor 5, Q 1 and the amplifier 20. Ru.
At this time, the charging convergence voltage Vcmax of the capacitor 7 is
It is clear that the potential difference between the first power supply potential and the output potential of the amplifier 1 of the power supply circuit 30 is V 1 .
Q2と、増幅器１の接続関係からV1は以下の様
に求められる。 From the connection relationship between Q 2 and amplifier 1, V 1 is determined as follows.
すなわち、IDQ2：Q2のドレイン電流
βQ2：Q2のβ
VTQ2：Q2のVT
Vref：第３電源電圧（基準電圧）
とすると
IDQ2＝βQ2／２（V1−VTQ2）2 ……
R2・IDQ2＝Vref ……
である。式より
V1＝VTQ2＋√2DQ2 Q2 ……′
を得、′式と式より
V1＝VTQ2＋√（2 Q2） ……
を得る。よつてコンデンサＣの充電収束電圧
Vcmaxは
Vcmax＝VTQ2＋√2 Q2 ……
となる。 In other words, I DQ2 : Drain current of Q 2 β Q2 : β of Q 2 V TQ2 : V T of Q 2 Vref: Third power supply voltage (reference voltage) I DQ2 = β Q2 /2 (V 1 − V TQ2 ) 2 ...R 2・I DQ2 = Vref... From the formula, we obtain V 1 = V TQ2 +√2 DQ2 Q2 ……′, and from the formula and formula, we obtain V 1 = V TQ2 +√( 2 Q2 )…. Therefore, the charging convergence voltage of capacitor C
Vcmax is Vcmax=V TQ2 +√ 2 Q2 ...
電流出力回路３２の出力電流端子１３から流れ
る出力電流値Ioutは以下のように求められる。 The output current value Iout flowing from the output current terminal 13 of the current output circuit 32 is determined as follows.
Iout＝βQ3／２（Vcmax−VTQ3）2 ……
式に式を代入し、
Iout＝βQ3／２（√2 Q2＋ΔVT）2……
ただし、ΔVT＝VTQ2−VTQ3
式において、ΔVTは、Q2とQ3のVT差であり、
同一ペレツト内に、Q2とQ3を作つた場合には
ΔVTはほぼゼロになり、式は、以下の様にな
る。 Iout=β Q3 /2 (Vcmax−V TQ3 ) 2 ... Substitute the formula into the equation, Iout=β Q3 /2 (√ 2 Q2 + ΔV T ) 2 ...
However, in the formula ΔV T =V TQ2 −V TQ3 , ΔV T is the V T difference between Q 2 and Q 3 ,
When Q 2 and Q 3 are made in the same pellet, ΔV T becomes almost zero, and the equation becomes as follows.
Iout＝Vref／2R2・βQ3／βQ2 ……
式により、出力電流値Ioutは、VTやβのば
らつきや、温度特性の影響を受けない事が判か
る。 Iout = Vref / 2R 2 · β Q3 / β Q2 ... From the formula, it can be seen that the output current value Iout is not affected by variations in V T and β or temperature characteristics.
本発明によれば振幅制御信号が供給されている
出力電流回路の出力電流値は、これに用いる
MOSトランジスタのしきい値電圧VTやβのばら
つきや温度特性の影響を受けない振幅制御信号発
生回路が得られる。 According to the present invention, the output current value of the output current circuit to which the amplitude control signal is supplied is
It is possible to obtain an amplitude control signal generation circuit that is not affected by variations in the threshold voltage V T or β of MOS transistors or by temperature characteristics.
第１図は従来の振幅制御信号発生回路の一例の
回路図、第２図は本発明の一実施例の回路図であ
る。
１……Q1のゲート電極、２……Q1のドレイン
電極、３……Q1のソース電極、４……Q1のバツ
クゲート、５……充電抵抗Ｒ、６……放電抵抗
RD、７……コンデンサＣ、８……第１電源端子、
９……出力信号端子、１４……増幅器２０の正相
入力端子、１５……増幅器２０の逆相入力端子、
１６……増幅器２０の出力端子、１７……第２電
源端子、１８……第３電源端子、１９……抵抗
R2，２０……増幅器、２１……Q2のゲート電極、
２２……Q2のソース電極、２３……Q2のドレイ
ン電極、２４……Q2のバツクゲート、３０……
電源回路、３１……充放電回路、３２……出力電
流回路、S1……Q1のソース電極とバツクゲート
との接続点、VC……振幅制御信号。
FIG. 1 is a circuit diagram of an example of a conventional amplitude control signal generating circuit, and FIG. 2 is a circuit diagram of an embodiment of the present invention. 1... Gate electrode of Q 1 , 2... Drain electrode of Q 1 , 3... Source electrode of Q 1 , 4... Back gate of Q 1 , 5... Charging resistance R, 6... Discharging resistance
R D , 7... Capacitor C, 8... First power supply terminal,
9... Output signal terminal, 14... Positive phase input terminal of amplifier 20, 15... Negative phase input terminal of amplifier 20,
16...Output terminal of amplifier 20, 17...Second power supply terminal, 18...Third power supply terminal, 19...Resistor
R 2 , 20...amplifier, 21...gate electrode of Q 2 ,
22... Source electrode of Q 2 , 23... Drain electrode of Q 2 , 24... Back gate of Q 2 , 30...
Power supply circuit, 31...charging/discharging circuit, 32...output current circuit, S1 ...connection point between the source electrode of Q1 and the back gate, Vc ...amplitude control signal.
Claims (1)
ンデンサの一端を接続し、該コンデンサの他端と
第１導電型MOSトランジスタのドレイン電極と
を充電抵抗を介して接続し、前記第１導電型
MOSトランジスタのソース電極とバツクゲート
との接続点を増幅器の出力端子に接続し、第２導
電型MOSトランジスタのソース電極及びバツク
ゲートを前記第１電源に接続し、前記第２導電型
MOSトランジスタのゲート電極を前記増幅器の
出力端子に接続し、前記第２導電型MOSトラン
ジスタのドレイン電極に前記増幅器の正相入力端
子と抵抗の一端を接続し、該抵抗の他端を第２電
源に接続し、前記増幅器の逆相入力端子を前記第
２電源に対して基準電圧を有する第３電源に接続
し、ソース電極を前記第１電源に接続する第２導
電型の電流出力用MOSトランジスタのゲート電
極に前記コンデンサの他端を接続して振幅制御信
号を供給し、前記第１導電型MOSトランジスタ
のゲート電極にスイツチ信号を入力してスイツチ
動作させて前記電流出力用MOSトランジスタの
ドレイン電流を制御する事を特徴とする振幅制御
信号発生回路。1 Connect one end of a capacitor connected in parallel with a discharge resistor to a first power supply, connect the other end of the capacitor and the drain electrode of a first conductivity type MOS transistor via a charging resistor, and mold
The connection point between the source electrode and the back gate of the MOS transistor is connected to the output terminal of the amplifier, the source electrode and the back gate of the second conductive type MOS transistor are connected to the first power supply, and the second conductive type MOS transistor is connected to the first power source.
The gate electrode of the MOS transistor is connected to the output terminal of the amplifier, the drain electrode of the second conductivity type MOS transistor is connected to the positive phase input terminal of the amplifier and one end of a resistor, and the other end of the resistor is connected to a second power source. a current output MOS transistor of a second conductivity type, the negative-phase input terminal of the amplifier is connected to a third power supply having a reference voltage with respect to the second power supply, and the source electrode is connected to the first power supply. The other end of the capacitor is connected to the gate electrode of the first conductivity type MOS transistor to supply an amplitude control signal, and a switch signal is input to the gate electrode of the first conductivity type MOS transistor to operate the switch to control the drain current of the current output MOS transistor. An amplitude control signal generation circuit characterized by controlling.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58128423A JPS6020621A (en) | 1983-07-14 | 1983-07-14 | Amplitude control signal generating circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58128423A JPS6020621A (en) | 1983-07-14 | 1983-07-14 | Amplitude control signal generating circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6020621A JPS6020621A (en) | 1985-02-01 |
| JPH0322732B2 true JPH0322732B2 (en) | 1991-03-27 |
Family
ID=14984388
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58128423A Granted JPS6020621A (en) | 1983-07-14 | 1983-07-14 | Amplitude control signal generating circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6020621A (en) |
-
1983
- 1983-07-14 JP JP58128423A patent/JPS6020621A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6020621A (en) | 1985-02-01 |
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