JPH0322755B2 - - Google Patents

Info

Publication number
JPH0322755B2
JPH0322755B2 JP56149168A JP14916881A JPH0322755B2 JP H0322755 B2 JPH0322755 B2 JP H0322755B2 JP 56149168 A JP56149168 A JP 56149168A JP 14916881 A JP14916881 A JP 14916881A JP H0322755 B2 JPH0322755 B2 JP H0322755B2
Authority
JP
Japan
Prior art keywords
region
conductivity type
substrate
layer
photoelectric conversion
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP56149168A
Other languages
Japanese (ja)
Other versions
JPS5850874A (en
Inventor
Hiromitsu Shiraki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP56149168A priority Critical patent/JPS5850874A/en
Publication of JPS5850874A publication Critical patent/JPS5850874A/en
Publication of JPH0322755B2 publication Critical patent/JPH0322755B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10FINORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F39/00Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
    • H10F39/10Integrated devices
    • H10F39/12Image sensors
    • H10F39/15Charge-coupled device [CCD] image sensors
    • H10F39/153Two-dimensional or three-dimensional array CCD image sensors

Landscapes

  • Transforming Light Signals Into Electric Signals (AREA)
  • Solid State Image Pick-Up Elements (AREA)

Description

【発明の詳細な説明】 本発明は電荷転送装置を用いた固体撮像装置に
関するものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a solid-state imaging device using a charge transfer device.

電荷転送装置を用いた撮像装置には大きく分け
てフレーム転送方式とインターライン転送方式が
ありそれらは固体撮像装置の特徴である小型、軽
量、低消費電力、高信頼性といつた使い易さの面
の長所を柱に急速に発展している。電荷転送装置
を用いた撮像装置は特性面からは雑音、残像、焼
き付き等では現在使用されている撮像管や他の固
体撮像装置より優れているがブルーミングスミア
が大きいという大きな欠点を有している。また電
極配線が微細で複雑なために、配線間の断線、シ
ヨートが発生して歩留が悪くなる事も欠点であ
る。
Imaging devices using charge transfer devices can be broadly divided into frame transfer methods and interline transfer methods, and these methods take advantage of the characteristics of solid-state imaging devices, such as small size, light weight, low power consumption, high reliability, and ease of use. It is rapidly developing based on its strengths. In terms of characteristics, imaging devices using charge transfer devices are superior to currently used image pickup tubes and other solid-state imaging devices in terms of noise, afterimages, and burn-in, but they have the major drawback of large blooming smear. . Another drawback is that because the electrode wiring is fine and complicated, disconnections and shorts occur between the wirings, resulting in poor yield.

従来のインターライン転送方式による電荷転送
撮像装置は第1図に示すように同一電荷転送電極
群で駆動される複数列の垂直シフトレジスター1
00と、各垂直レジスターの一側に隣接しかつ互
に電気的に分離された光電変換部101と、垂直
シフトレジスターと光電変換部間の信号電荷の転
送を制御するトランスフアー電極102と、各垂
直シフトレジスターの一端に設けられた水平シフ
トレジスター103と水平レジスターの一端に設
けられた信号電荷を検出する装置104よりな
る。垂直シフトレジスターは端子106,107
よりパルスφ1,φ2によつて駆動され、トランス
フアーゲートは端子105からパルスφTによつ
て駆動される。
As shown in FIG. 1, a conventional charge transfer imaging device using an interline transfer method has multiple columns of vertical shift registers 1 driven by the same charge transfer electrode group.
00, a photoelectric conversion unit 101 adjacent to one side of each vertical register and electrically isolated from each other, a transfer electrode 102 that controls the transfer of signal charges between the vertical shift register and the photoelectric conversion unit, and It consists of a horizontal shift register 103 provided at one end of the vertical shift register and a device 104 for detecting signal charges provided at one end of the horizontal register. The vertical shift register is connected to terminals 106 and 107.
The transfer gate is driven by pulses φ 1 and φ 2 from terminal 105, and the transfer gate is driven by pulse φ T from terminal 105.

このようなインターライン転送方式による撮像
装置では光電変換部101に入射光量に応じて蓄
積された信号電荷はトランスフアーゲート102
を介してそれぞれ対応するシフトレジスター10
0へ転送される。垂直シフトレジスターへ信号電
荷を転送したのちトランスフアーゲートが閉じら
れ光電変換部101は次の周期(フイールドある
いはフレーム)の信号電荷を蓄積する。一方垂直
レジスター100に転送された信号電荷は並列に
垂直方向に転送され、各垂直レジスターの一水平
ラインごとに水平レジスター103に転送され
る。水平レジスターに送られた電荷は次に垂直シ
フトレジスターから信号電荷が転送されて来るま
でに水平方向に転送され電荷検出部104から時
系列の映像信号として外部にとりだされる。
In an imaging device using such an interline transfer method, signal charges accumulated in the photoelectric conversion unit 101 according to the amount of incident light are transferred to the transfer gate 102.
respectively corresponding shift registers 10 through
Transferred to 0. After the signal charges are transferred to the vertical shift register, the transfer gate is closed and the photoelectric conversion unit 101 accumulates the signal charges for the next period (field or frame). On the other hand, the signal charges transferred to the vertical registers 100 are transferred in parallel in the vertical direction, and are transferred to the horizontal registers 103 for each horizontal line of each vertical register. The charge sent to the horizontal register is transferred in the horizontal direction until the next signal charge is transferred from the vertical shift register, and is taken out from the charge detection section 104 as a time-series video signal.

このようなインターライン転送方式の典形的な
単位セルの上面図を第2図aに、第2図aの−
′線、−′線および−′線に沿つた断面
図をそれぞれ第2図b,cおよびdに示す。以下
の説明において同一番号で表わされる部分は同一
の構造をもち同一の働らきをする。第2図におい
て単位セルはP型半導体基板201の主面に薄い
絶縁膜202を介して二相駆動垂直レジスターの
蓄積領域215、バリアー領域214上にそれぞ
れ形成された電荷転送電極203,204、光電
変換部101から垂直レジスターへの信号電荷の
転送を制御するトランスフアーゲート電極102
および基板半導体201と該基板半導体と異なる
導電型を有するN型導電形層205で構成される
P−N接合よりなる光電変換部101よりなり
各々の光電変換部は隣接する垂直シフトレジスタ
ーや他の光電変換部から基板と同一導電形でかつ
高濃度の不純物領域207と厚い絶縁膜211の
二重層によつて電気的に分離されている。
A top view of a typical unit cell of such an interline transfer method is shown in FIG.
Cross-sectional views taken along the lines ', -' and -' are shown in Figures 2b, c and d, respectively. In the following description, parts denoted by the same numbers have the same structure and function the same. In FIG. 2, the unit cell includes charge transfer electrodes 203 and 204 formed on the main surface of a P-type semiconductor substrate 201 through a thin insulating film 202 on an accumulation region 215 of a two-phase drive vertical register, a barrier region 214, and a photovoltaic electrode. Transfer gate electrode 102 that controls the transfer of signal charges from the conversion unit 101 to the vertical register
and a photoelectric conversion section 101 made of a P-N junction composed of a substrate semiconductor 201 and an N-type conductivity type layer 205 having a conductivity type different from that of the substrate semiconductor, and each photoelectric conversion section is connected to an adjacent vertical shift register or other It is electrically separated from the photoelectric conversion section by a double layer of a high concentration impurity region 207 and a thick insulating film 211 that has the same conductivity type as the substrate.

また二つの転送電極203,204は互に絶縁
膜208で分離されている。また転送電極とトラ
ンスフアーゲート電極は絶縁膜213で分離され
ている。また光電変換部以外はたとえば金属層2
12で光しやへいされている。なお第2図aにお
いては光しやへい層は図示されていない。また絶
縁膜209は金属層による光しやへいの際に転送
電極203,204が短らくするのを防止してい
る。また210は埋込チヤネル電荷転送路を形成
するための基板と異つた導電型を有する層であ
り、212は二相駆動を実現するためにこの層中
に形成した基板と同じ導電型を有する層であるま
た一つの転送段を構成する転送電極203,20
4は配線216によつて結合されておりこの例の
ように垂直レジスターに二相駆動を用いる場合に
は転送電極203,204を対として一つおきに
別々の転送パルスφ1,φ2が印加される。
Further, the two transfer electrodes 203 and 204 are separated from each other by an insulating film 208. Further, the transfer electrode and the transfer gate electrode are separated by an insulating film 213. In addition, for example, the metal layer 2 other than the photoelectric conversion part
It is illuminated at 12. Note that in FIG. 2a, the light-resistant layer is not illustrated. Furthermore, the insulating film 209 prevents the transfer electrodes 203 and 204 from being shortened when the metal layer shields the light. Further, 210 is a layer having a conductivity type different from that of the substrate for forming a buried channel charge transfer path, and 212 is a layer having the same conductivity type as the substrate formed in this layer to realize two-phase drive. Transfer electrodes 203 and 20 constituting another transfer stage
4 are connected by a wiring 216, and when using two-phase drive for the vertical register as in this example, separate transfer pulses φ 1 and φ 2 are applied to every other pair of transfer electrodes 203 and 204. be done.

このような従来の電荷転送装置では、転送電極
203,204およびトランスフアーゲート電極
102が凹凸のある面上に配線されるため断線を
起し易い。また転送電極203,204は第2図
aに矢印で示した領域Aで細くなるため断線を起
したり配線抵抗が高くなつて高い周波数での電荷
転送が困難になる。また電極間相互や電極と光し
やへい層のオーバーラツプが多いためにそれらの
間がしばしば短絡する。また三層の電極配線と一
層の光しやへい層を必要とするため製造工程が多
くなり歩留りが悪くなる。更に構造が複雑で製造
時に種々のマージン(目合セ、オーバラツプ等)
を必要とするため微細化や多素子化が困難であつ
たり受光領域の開口率が小さくなる欠点があつ
た。
In such a conventional charge transfer device, the transfer electrodes 203, 204 and the transfer gate electrode 102 are wired on an uneven surface, so that wire breakage is likely to occur. Furthermore, since the transfer electrodes 203 and 204 become thinner in a region A indicated by an arrow in FIG. 2a, wire breakage occurs or wiring resistance increases, making it difficult to transfer charges at high frequencies. Furthermore, since there is a large overlap between the electrodes and between the electrodes and the photoresist layer, short circuits often occur between them. Furthermore, since three layers of electrode wiring and one layer of light-shielding layer are required, the number of manufacturing steps is increased, resulting in poor yield. Furthermore, the structure is complex and various margins (meeting, overlap, etc.) are required during manufacturing.
The disadvantages are that it is difficult to miniaturize and increase the number of elements, and the aperture ratio of the light-receiving area is small.

本発明の目的は上記の欠点を無くした新しい構
造の電荷転送装置とその駆動法を提供することに
ある。
SUMMARY OF THE INVENTION An object of the present invention is to provide a charge transfer device with a new structure that eliminates the above-mentioned drawbacks and a method for driving the same.

本発明によれば半導体基板の主面に該半導体基
板と反対導電型の層を設け、その層上に二次元的
に配列した光電変換蓄積領域と複数個の電荷転送
レジスター領域と、基板と同じ導電型の領域とそ
の上の基板と反対の導電型の領域とからなり前記
二領域の間の電荷の移動を制御するトランスフア
ーゲート領域と水平レジスター領域と電荷検出領
域よりなり、この垂直方向電極下に転送方向に交
互に並んだ基板と同じ導電型の蓄積領域とバリア
ー領域が設けられ、蓄積領域の不純物濃度はバリ
アー領域のそれより高く、トランスフアーゲート
領域を間にはさんで一つの光電変換蓄積領域に一
つの蓄積領域が対応し、蓄積領域とバリアー領域
は一つおきに基板と反対導電型の層を表面に有
し、この層のない蓄積領域からこの層のある蓄積
領域へ向かつて電荷が転送される固体撮像装置に
おいて垂直レジスター領域の駆動電極が一個の垂
直方向電極よりなることを特徴とする固体撮像装
置が得られる。
According to the present invention, a layer having a conductivity type opposite to that of the semiconductor substrate is provided on the main surface of the semiconductor substrate, and a photoelectric conversion storage region and a plurality of charge transfer register regions arranged two-dimensionally on the layer, the same as the substrate. This vertical electrode consists of a conductivity type region and a conductivity type region opposite to that of the substrate above it, a transfer gate region for controlling charge transfer between the two regions, a horizontal register region, and a charge detection region. Storage regions and barrier regions of the same conductivity type as the substrate are provided below, which are arranged alternately in the transfer direction, and the impurity concentration of the storage regions is higher than that of the barrier regions. One storage region corresponds to the conversion storage region, and every other storage region and barrier region have a layer on the surface of the conductivity type opposite to that of the substrate, and the direction is from the storage region without this layer to the storage region with this layer. A solid-state imaging device in which charge is transferred in the past is characterized in that the drive electrode in the vertical register region is composed of one vertical electrode.

さらに本発明によれば半導体基板の主面に該半
導体と反対導電型の層を設け、その層上に二次元
的に配置した光電変換蓄積領域と、一個の垂直方
向電極により駆動されこの垂直方向電極下に転送
方向に交互に並んだ基板と同じ導電型の蓄積領域
とバリアー領域が設けられ、蓄積領域の不純物濃
度はバリアー領域のそれより高く、トランスフア
ーゲート領域を間にはさんで一つの光電変換蓄積
領域に一つの蓄積領域が対応し、蓄積領域とバリ
アー領域は一つおきに基板と反対導電型の層を表
面に有する電荷転送垂直レジスターと、基板と同
じ導電型の領域とその上の基板と反対導電型の領
域とからなるトランスフアーゲート領域と、水平
レジスターと電荷検出領域を設けてなる固体撮像
装置において光電変換時には前記半導体基板と前
記反対導電型層の間に大きな逆バイアス電圧を印
加し、該逆バイアス電圧を減ずることによつて光
電変換蓄積領域に蓄わえられた信号電荷を前記垂
直レジスターに移すことを特徴とする固体撮像装
置の駆動法が得られる。
Furthermore, according to the present invention, a layer of conductivity type opposite to that of the semiconductor is provided on the main surface of the semiconductor substrate, and a photoelectric conversion storage region is arranged two-dimensionally on the layer, and a photoelectric conversion storage region is driven by a single vertical electrode, and Under the electrodes, storage regions and barrier regions of the same conductivity type as the substrate are provided alternately in the transfer direction, and the impurity concentration of the storage regions is higher than that of the barrier regions. One storage region corresponds to the photoelectric conversion storage region, and every other storage region and barrier region has a charge transfer vertical register having a layer of conductivity type opposite to that of the substrate on its surface, and a region of the same conductivity type as the substrate and a layer above it. A large reverse bias voltage is applied between the semiconductor substrate and the opposite conductivity type layer during photoelectric conversion in a solid-state imaging device including a transfer gate region consisting of a substrate and a region of opposite conductivity type, a horizontal register, and a charge detection region. A method for driving a solid-state imaging device is obtained, characterized in that the signal charge stored in the photoelectric conversion storage region is transferred to the vertical register by applying the reverse bias voltage and reducing the reverse bias voltage.

前記本発明では従来構造ではきわめて複雑な構
造をしていた垂直レジスターとトランスフアーゲ
ート領域が垂直方向の単一の電極によつて形成出
来るので前述の欠点を克服出来る。また後述する
ように本発明は残像の少ないフイールド蓄積モー
ドで駆動出来る。
In the present invention, since the vertical register and transfer gate region, which had a very complicated structure in the conventional structure, can be formed by a single vertical electrode, the above-mentioned drawbacks can be overcome. Furthermore, as will be described later, the present invention can be driven in field accumulation mode with less afterimage.

次に本発明の実施例について図面を用いて具体
的に説明する。以後の本発明の実施例の説明はN
チヤネルの半導体装置について行うが、本発明は
Pチヤネルの場合についても適用出来ることは云
うまでもない。
Next, embodiments of the present invention will be specifically described using the drawings. The following description of the embodiments of the present invention is provided by N.
Although the present invention will be described with reference to a P-channel semiconductor device, it goes without saying that the present invention can also be applied to a P-channel semiconductor device.

第3図および第4図は本発明の構造の一実施例
を示し第3図は全体図、第4図はその単位セルの
構造を示す。第4図においてaは単位セルの上面
図、b図およびc図はa図の−′線、−
′線に沿つた断面図を示している。従来構造と
の大きな違いは第3図および第4図より解るよう
に従来構造におけるトランスフアーゲートはなく
垂直レジスター電極が薄い酸化膜202の上に形
成された一層の垂直方向電極301に置き換えら
れていることである。
3 and 4 show an embodiment of the structure of the present invention, FIG. 3 shows the overall view, and FIG. 4 shows the structure of a unit cell thereof. In Figure 4, a is a top view of the unit cell, figures b and c are the -' line of figure a, -
A cross-sectional view taken along the line ′ is shown. The major difference from the conventional structure is that, as can be seen from FIGS. 3 and 4, there is no transfer gate in the conventional structure, and the vertical register electrode is replaced with a single layer of vertical electrodes 301 formed on a thin oxide film 202. It is that you are.

もう一つの大きな違いは活性領域がN基板41
2上のPウエル413中に作れていることであ
る。次にこれらの部分の構造と動作について説明
する。まず、垂直レジスター部は四つの領域40
1,402,403,404よりなりその不純物
分布はそれぞれ異つている。すなわち401,4
02に対応する部分ではPウエル413上にそれ
ぞれN領域407(ドナー濃度N4)および40
6(ドナー濃度N3)が形成されており、更にそ
の上にP+領域405が形成されている。また4
03,404に対応する部分はPウエル413上
にそれぞれN領域409(ドナー濃度N2)およ
び408(ドナ濃度N1)が形成されている。
Another major difference is that the active region is an N substrate 41
This is created in the P well 413 on the top of the second well. Next, the structure and operation of these parts will be explained. First, the vertical register section has four areas 40.
1,402, 403, and 404, each having a different impurity distribution. i.e. 401,4
In the part corresponding to 02, N regions 407 (donor concentration N 4 ) and 40
6 (donor concentration N 3 ), and a P + region 405 is further formed thereon. Also 4
In the portions corresponding to 03 and 404, N regions 409 (donor concentration N 2 ) and 408 (donor concentration N 1 ) are formed on the P well 413, respectively.

Pウエル413のアクセプター濃度は1×
1014/cm3程度であり、N領域407,409のド
ナー濃度は1×1015/cm3程度、N領域408,4
06のドナー濃度は5×1014/cm3程度、P+領域4
05のアクセプター濃度は5×1015/cm3程度であ
る。また光電変換領域414のドナー濃度は1×
1015cm-3程度で深さは約3μmである。またトラン
スフアーゲート部は薄い島状領域上にn領域41
1が設けられ更にその上にP領域410が設けて
成つている。n領域411の厚さは約1.5μmで不
純物濃度は1×1015/cm3程度であり、p領域41
0の厚さ約2μm、不純物濃度は5×1015/cm3程度
である。
The acceptor concentration in P-well 413 is 1×
The donor concentration in the N regions 407 and 409 is about 1×10 15 /cm 3 , and the donor concentration in the N regions 408 and 4 is about 1×10 15 /cm 3 .
The donor concentration of 06 is about 5×10 14 /cm 3 , P + region 4
The acceptor concentration of 05 is about 5×10 15 /cm 3 . In addition, the donor concentration of the photoelectric conversion region 414 is 1×
The depth is about 10 15 cm -3 and about 3 μm. In addition, the transfer gate portion is formed by forming an n region 41 on a thin island-like region.
1 is provided, and furthermore, a P region 410 is provided thereon. The thickness of the n region 411 is about 1.5 μm and the impurity concentration is about 1×10 15 /cm 3 .
The thickness of the layer 0 is about 2 μm, and the impurity concentration is about 5×10 15 /cm 3 .

ドナー濃度N1〜N4を適切に選ぶと、これらの
N領域をデプレツシヨン(depletion)にしたと
きのその中の最大電位naxと垂直方向電極電圧φP
の関係を第5図501〜504のようにすること
が出来る。即ち領域401のnaxと領域402の
naxはP+領域405が存在するためにφPに無関
係でありかつ領域401のnaxは領域402の
naxより大になつている。また領域403のnax
と領域404のnaxはP領域がないためφPの関数
となりφPが高いとき(φP=φH Pのとき)には共に
領域401,402のnaxより高くなりφPが低い
(φP=φL Pのとき)ときには共に低くなつている。
またφPにかゝわらず領域403のnaxは404の
naxより高くなつている。領域401と403は
シフトレジスターの蓄積領域であり領域402と
404はバリアー領域である。トランスフアーゲ
ートに対応する領域はPウエル上にN領域411
が形成されその上にP領域410が形成されてい
る。この部分の動作は領域401,402と原理
的に同じであるがデバイスの動作上重要であるの
でくわしく説明しておく。
If the donor concentrations N 1 to N 4 are appropriately selected, the maximum potential nax and vertical electrode voltage φ P when these N regions are in depletion are
The relationships can be made as shown in FIG. 5, 501 to 504. In other words, nax in area 401 and area 402
nax is unrelated to φ P due to the existence of P + region 405, and nax in region 401 is
It's getting bigger than nax . Also area 403 nax
Since there is no P region, nax in region 404 is a function of φ P , and when φ P is high (when φ P = φ H P ), both are higher than nax in regions 401 and 402, and φ P is low (φ P = φ L P ) Sometimes both are low.
Also, regardless of φ P, the nax of area 403 is the same as that of 404.
It is higher than nax . Areas 401 and 403 are storage areas of the shift register, and areas 402 and 404 are barrier areas. The region corresponding to the transfer gate is an N region 411 on the P well.
is formed, and a P region 410 is formed thereon. The operation of this part is the same in principle as areas 401 and 402, but will be explained in detail since it is important for the operation of the device.

第6図aはトランスフアーゲートに対応する領
域の厚さ方向の構造、第6図bはトランスフアー
ゲート対応領域のSiO2膜表面の電位VTGと深さ方
向の電位分布の関係を示している。このSiO2
には電極はないがその表面の電位はφPの振巾の
範囲で変化する可能性がある。VTGが負、あるい
は正で小さいときにはP領域410は空乏化しな
いのでN領域411中の最大電位TG
Figure 6a shows the structure in the thickness direction of the region corresponding to the transfer gate, and Figure 6b shows the relationship between the potential V TG on the surface of the SiO 2 film in the region corresponding to the transfer gate and the potential distribution in the depth direction. There is. Although there is no electrode on this SiO 2 surface, the potential on its surface may change within the range of the amplitude of φ P. When V TG is negative or positive and small, the P region 410 is not depleted, so the maximum potential TG in the N region 411

Claims (1)

【特許請求の範囲】 1 半導体基板の主面に該半導体基板と反対導電
型の層を設け、その層上に二次元的に配列した光
電変換蓄積領域と複数個の電荷転送垂直レジスタ
ー領域と、基板と同じ導電型の領域とその上の基
板と反対の導電型の領域とからなり前記二領域の
間の電荷の移動を制御するトランスフアーゲート
領域と水平レジスター領域と電荷検出領域を設け
た固体撮像装置であつて、電荷転送垂直レジスタ
ー領域の駆動電極が一個の垂直方向電極よりな
り、この垂直方向電極下に転送方向に交互に並ん
だ基板と同じ導電型の蓄積領域とバリアー領域が
設けられ、蓄積領域の不純物濃度はバリアー領域
のそれより高く、トランスフアゲート領域を間に
はさんで一つの光電変換蓄積領域に一つの蓄積領
域が対応し、蓄積領域とバリアー領域は一つおき
に基板と反対導電型の層を表面に有し、この層の
ない蓄積領域からこの層のある蓄積領域へ向かつ
て電荷が転送されることを特徴とする固体撮像装
置。 2 半導体基板の主面に該半導体基板と反対導電
型の層を設け、その層上に二次元的に配置した光
電変換蓄積領域と、一個の垂直方向電極により駆
動されこの垂直方向電極下に転送方向に交互に並
んだ基板と同じ導電型の蓄積領域とバリアー領域
が設けられ、蓄積領域の不純物濃度はバリアー領
域のそれより高く、トランスフアゲート領域を間
にはさんで一つの光電変換蓄積領域に一つの蓄積
領域が対応し、蓄積領域とバリアー領域は一つお
きに基板と反対導電型の層を表面に有する電荷転
送垂直レジスターと、基板と同じ導電型の領域と
その上の基板と反対導電型の領域とからなるトラ
ンスフアーゲート領域と、水平レジスターと電荷
検出領域を設けてなる固体撮像装置の駆動法であ
つて、光電変換時には前記半導体基板と前記反対
導電型層の間に大きな逆バイアス電圧を印加し、
該逆バイアス電圧を減することによつて光電変換
蓄積領域に蓄えられた信号電荷を前記電荷転送垂
直レジスターに移すことを特徴とする固体撮像装
置の駆動法。
[Scope of Claims] 1. A layer having a conductivity type opposite to that of the semiconductor substrate is provided on the main surface of the semiconductor substrate, and a photoelectric conversion storage region and a plurality of charge transfer vertical register regions are arranged two-dimensionally on the layer; A solid comprising a region of the same conductivity type as the substrate and a region thereon of the conductivity type opposite to that of the substrate, and provided with a transfer gate region, a horizontal register region, and a charge detection region for controlling charge transfer between the two regions. In the imaging device, the driving electrode of the charge transfer vertical register region is composed of a single vertical electrode, and storage regions and barrier regions of the same conductivity type as the substrate are provided below the vertical electrode and arranged alternately in the transfer direction. , the impurity concentration in the storage region is higher than that in the barrier region, one storage region corresponds to one photoelectric conversion storage region with a transfer gate region in between, and every other storage region and barrier region are separated by a substrate. 1. A solid-state imaging device having a layer of opposite conductivity type on its surface, in which charge is transferred from an accumulation region without this layer to an accumulation region with this layer. 2. A layer of conductivity type opposite to that of the semiconductor substrate is provided on the main surface of the semiconductor substrate, and a photoelectric conversion and storage region is arranged two-dimensionally on the layer, and a photoelectric conversion storage region is driven by one vertical electrode and transferred under this vertical electrode. Storage regions and barrier regions of the same conductivity type as the substrate are arranged alternately in the direction, the impurity concentration of the storage region is higher than that of the barrier region, and a transfer gate region is sandwiched between them to form one photoelectric conversion storage region. One storage region corresponds to the other, and every other storage region and barrier region are charge transfer vertical registers having a layer on the surface of a conductivity type opposite to that of the substrate, and a region having the same conductivity type as the substrate and an overlying region having a conductivity opposite to that of the substrate. A driving method of a solid-state imaging device comprising a transfer gate region consisting of a mold region, a horizontal register and a charge detection region, wherein a large reverse bias is applied between the semiconductor substrate and the opposite conductivity type layer during photoelectric conversion. Apply voltage,
A method for driving a solid-state imaging device, characterized in that the signal charge stored in the photoelectric conversion storage region is transferred to the charge transfer vertical register by reducing the reverse bias voltage.
JP56149168A 1981-09-21 1981-09-21 Solid-state imaging device and its driving method Granted JPS5850874A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56149168A JPS5850874A (en) 1981-09-21 1981-09-21 Solid-state imaging device and its driving method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56149168A JPS5850874A (en) 1981-09-21 1981-09-21 Solid-state imaging device and its driving method

Publications (2)

Publication Number Publication Date
JPS5850874A JPS5850874A (en) 1983-03-25
JPH0322755B2 true JPH0322755B2 (en) 1991-03-27

Family

ID=15469277

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56149168A Granted JPS5850874A (en) 1981-09-21 1981-09-21 Solid-state imaging device and its driving method

Country Status (1)

Country Link
JP (1) JPS5850874A (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4525235B2 (en) * 2004-08-09 2010-08-18 セイコーエプソン株式会社 Solid-state imaging device and driving method thereof
JP4389720B2 (en) 2004-08-09 2009-12-24 セイコーエプソン株式会社 Solid-state imaging device and driving method of solid-state imaging device
JP4389737B2 (en) 2004-09-22 2009-12-24 セイコーエプソン株式会社 Solid-state imaging device and driving method thereof

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS54124480U (en) * 1978-02-20 1979-08-31

Also Published As

Publication number Publication date
JPS5850874A (en) 1983-03-25

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