JPH0322763A - Clamping circuit - Google Patents

Abstract

PURPOSE:To control a clamp voltage to a constant value by providing a comparing and output circuit which compares a sampled value of the output video signal of an A/D converter with a reference value and outputs a signal increased or decreased from an cutput signal generated a constant period before by certain width according to which is larger. CONSTITUTION:In a control loop, the clamp voltage is controlled by using a ROM 10 as the comparing and output circuit which compares the sampled value of the output video signal of the A/D converter 8 with the reference value and outputs the signal increased or decreased from the output signal obtained the constant period before by the certain width according to the comparison result. Therefore, the clamp voltage can be converged on the reference digital value without being affected by a circuit element nor variation in source voltage. Consequently, the clamp voltage is controlled to the constant value.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a clamp circuit that always maintains the clamp voltage of a video signal at a constant level. [Prior art] Figure 4 shows a conventional clamp circuit. In the figure, 1 is a buffer amplifier, 2 is a capacitor, 3.4 is a resistor that determines the clamp voltage, 5 is a clamp voltage generation circuit, 6 is a sample hold circuit, and 7 is a pulse that supplies clamping to the sample hold circuit 6. 8 is an A/D converter that converts the clamped video signal into a digital value. Next, we will explain the operation. Analog input video signal a is amplified by buffer amplifier 1, and DC power is removed by capacitor 2. Further, the clamp voltage is determined by a resistor 3.4, and is led to a sample and hold circuit 6 through a clamp voltage generation circuit 5. On the other hand, the analog input video signal a is separately guided to a clamp pulse generation circuit 7 which separates the horizontal synchronization part and generates pulses of appropriate width and timing. The sample and hold circuit 6 is supplied with the clamp pulse generated by the clamp pulse generation circuit 7, and the input video signal a generated by the output of the capacitor 2 is clamped by this timing, and converted into a digital value by the A/D converter 8. It is converted to . [Problems to be Solved by the Invention] Conventional clamp circuits are configured as described above, so due to variations in circuit elements, fluctuations in power supply voltage, etc.
The clamp voltage may deviate from the reference value.
The problem was that adjustments were required each time. This invention was made to solve the above-mentioned problems, and its purpose is to provide a clamp circuit that can always control the clamp voltage to a constant value regardless of variations in circuit elements or fluctuations in power supply voltage. Suppose that [Means for Solving the Problems] A clamp circuit according to the present invention compares a sampling value of an output video signal of an A/D converter with a reference value, and depending on the difference, a sampling value of an output video signal of a certain period before. This is a control loop that controls the clamp voltage using a comparison output circuit that outputs a signal that increases or decreases by a certain width. [Operation] In this invention, the sampling value of the output video signal of the A/D converter is compared with a reference value, and depending on the difference,
Since we have provided a comparison output circuit that outputs a signal that is increased or decreased by a certain width from the output signal a certain period before, it is possible to eliminate variations in circuit elements and fluctuations in power supply voltage, and as a result, the clamp voltage can be kept at a constant value. It can be controlled to [
Embodiment] An embodiment of the present invention will be described below with reference to the drawings. In FIG. 1, reference numeral 9 denotes a first latch circuit that samples a predetermined portion of the video signal after A/D conversion at a predetermined period;
O is a ROM as a comparison output circuit that compares the sampling signal of the first latch circuit 9 with a reference value, and outputs a signal that is increased or decreased by a certain width from the output signal a certain period before, according to the difference; 11 is a second latch circuit that latches the output of the ROMIO; 12 is a D/A converter that converts the output of the second latch circuit 10 into an analog value; 13 is a level compressor for the output of the D/A converter 12; This is a level compression shift circuit that shifts, and in this example, it is implemented using a resistor element. 14 is the first. This is a latch pulse generation circuit which outputs latch pulses c and d at appropriate timings to the second latch circuit 9.11.Other parts equivalent to the conventional example shown in FIG. 4 are designated by the same reference numerals. Next, we will explain the operation. In FIG. 1, an input video signal a passes through a buffer amplifier l, has its direct current component removed by a capacitor 2, and is clamped to a certain value through a sample-and-hold circuit 6. Thereafter, it is converted into a digital value by the A/D converter 8, and becomes the output video signal b. On the other hand, the input video signal a is supplied to the latch pulse generation circuit l4.
As a result, the vertical synchronization part is separated and an appropriate rough tip C with a period of l field (1/60 seconds) that can sample the pedestal part of the output video signal b, and an offset of a certain period with respect to the latch pulse C are used. Outputs the latch pulse d. The pedestal portion of the output video signal b is latched by the first latch circuit 9 at the timing of the latch pulse C, and becomes the ROMIO address. R
The output of OMIO is input to the second latch circuit 11 and latched by the latch pulse d. Figure 2 shows the relationship between this input video signal and both latch pulses. Further, the output f of the second latch circuit 11 is input to the D/A converter l2, and is returned to the address of the ROMIO.
Then, the output e of the first latch circuit 9, that is, the current value, is compared with the reference pedestal value, and if the output e of the l-th latch circuit 9 is smaller than the reference value, the output e of the second latch circuit 11 is Output f, I than the value one field ago
Outputs a value that is larger by the LSB. Similarly, if the output e of the first latch circuit 9 is larger than the reference value, the second
A value smaller than the output f of the latch circuit l1 by I LSB is output. The output of the D/A converter l2 is level compressed by the level compression shift circuit 13 so that the conversion width per bit is smaller than the resolution per bit of the A/D converter 8, or the convergence value is The voltage is level-shifted so that it swings toward the center, and is supplied as a clamp voltage through a clamp voltage generation circuit 5 and a sample-and-hold circuit 6. FIG. 3 is a diagram showing this situation, in which the first latch circuit 9
Let the value of the output e of the second latch circuit 11 be X, and the value of the output f of the second latch circuit 11 be y. Let the reference clamp value be z,,zs*X. The value of y at this time is y e , and the output value of R OM 1 0 is 2. For example, if Z is at position A, it is larger than xa, so in the next field, a value one smaller than this time Z = y @ + 1 is output (position A)
．． Next, X is X. If it becomes +1 (position C), this is still X. Since the value is larger than , the value Z = y *, which is one smaller than the previous value, that is, the value before l field, is output (factor t). As described above, X eventually converges to the value of X6 and converges to Z = y o. In this way, in this embodiment, a signal obtained by sampling a predetermined portion of the output video signal of the A/D converter at a predetermined period,
An RO that compares the reference value and outputs a signal that is increased or decreased by a certain width from the output signal a certain period ago, depending on the difference.
By incorporating a loop circuit that controls the clamp voltage using M, it is possible to eliminate fluctuations in the clamp voltage due to variations in circuit elements, etc., and to control the clamp voltage to a constant value. In the above embodiment, the latch pulse is a pulse with a one-field period, but it may be a pulse with another period.
Further, although a ROM is used for the comparison output circuit, other gates may also be used, and even if a microcomputer or the like is used, the same effect can be obtained. Also, although a resistive element is used in the level compression shift circuit, it may be used in combination with other active elements. [Effects of the Invention] As described above, according to the clamp circuit according to the present invention,
The clamp voltage is determined using a comparison output circuit that compares the sampling value of the output video signal of the A/D converter with a reference value, and outputs a signal that is increased or decreased by a certain width from the output signal a certain period before, according to the difference. Since we have designed a control loop to control the voltage, the clamp voltage can be converged to the reference digital value without being affected by fluctuations in circuit elements or power supply voltage, and as a result, the clamp voltage can be controlled to a constant value. It has the effect of being able to

[Brief explanation of drawings]

FIG. 1 is a diagram showing a clamp circuit according to an embodiment of the present invention, FIG. 2 is a diagram showing the relationship between input video signal and latch pulse timing, and FIG. 3 is a diagram showing the operation of the above embodiment.
Figure 4 shows a conventional clamp circuit. 2 is a capacitor, 3.4 is a resistor, 9 is a first latch circuit, 10 is a ROM (comparison output circuit), 11 is a second latch circuit, 12 is a D/A converter, l3 is a level compression shift circuit, 14 is a latch pulse generation circuit. Note that the same reference numerals in the figures indicate the same or equivalent parts.

Claims (1)

[Claims] (1) A clamp circuit configured to always maintain a clamp voltage of an input video signal at a constant level, which includes an A/D converter that converts the input video signal into a digital signal, and a predetermined portion of the digital signal at a predetermined period. A first latch circuit that samples, compares the sampled value with a reference value, and according to the difference,
A comparison output circuit that outputs a signal that is increased or decreased by a certain width from an output signal a certain period before, a second latch circuit that samples a predetermined portion of the output signal at a predetermined period, and converts the output of the latch circuit into an analog value. A D/A converter that converts into
A level compression shift circuit that compresses the level to below the resolution per bit of the D converter and shifts the level to a predetermined level; and a clamp voltage that sets the clamp voltage of the input video signal based on the output of the level compression shift circuit. A clamp circuit comprising a supply circuit.