JPH03292064A - Clamping circuit - Google Patents

Abstract

PURPOSE:To attain feedback with the excellent followup performance by converting a digital signal obtained through A/D conversion into an analog signal again, inputting the analog signal and a clamp voltage converted into an analog signal to a control voltage generating circuit to regulate the deviation of a DC component based on the difference. CONSTITUTION:When there exists any difference between a voltage relating to an output signal VA of an amplifier 2 and a clamp voltage designated by a digital signal CL relating to a clamp level for a period when a clamp pulse CP is at an H level, a control voltage generating circuit 7 outputs a control voltage VDC so as to eliminate the difference and the control voltage VDC regulates a DC level of the amplified output signal VA of the amplifier 2. Then the control voltage generating circuit 7 latches a signal voltage when the clamp pulse CP is at an H level for a period when the clamp pulse CP is at an L level. Then the amplified output signal VA whose DC component is regulated based on the signal CL relating to the clamp level is obtained at an output terminal 2c of the amplifier 2.

Description

Detailed Description of the Invention (Industrial Application Field) This invention fixes a required portion of an image signal at a certain level, obtains an image signal with a DC component adjusted based on this fixed level, and The present invention relates to an improvement of a clamp circuit that can convert this image signal into a digital signal and output it.

(Conventional technology) FIG. 2 is a block diagram of a conventional clamp circuit.

The image signal VI input to the input terminal 11 is sent to the amplifier 12.
After being amplified by the A/
It is applied to the input terminal 14a of the D converter 140 and one terminal 15a of the analog switch 15. A clamp voltage VCL is applied to the other terminal 15b of the analog switch 15 from the voltage source 16. This analog switch 15 is configured to perform a switching operation based on a clamp pulse CP applied to a clamp control input terminal 17.

When the clamp pulse CP is at H level, the analog switch 15 is turned on, and the clamp voltage CL is applied to the input terminal 14a of the A/D converter 14. When clamp pulse CP is at L level, analog switch 15
is in the off state, and the input terminal 14a of the A/D converter 14
In this case, the output signal VA of the amplifier 12 is applied to the clamp voltage VCL.
A superimposed signal is applied. These signals are then converted into a digital output signal VD by the A/D converter 14 and output.

FIG. 8 is a block diagram showing another conventional example.

The image signal VI applied to the input terminal 21 is transmitted to the amplifier 22
After being amplified, the signal is input to the A/D converter 23. The amplifier 22 is configured to be able to vary the DC level of the amplified output signal VA based on the control voltage VDC applied to the DC level control terminal 22a.

The digital output signal VD from the A/D converter 23 is connected to one input terminal 24a of the subtracter 24, and the digital signal CL related to the clamp level is input to the other input terminal 24b of the subtracter 24. be done. The subtracter 24 outputs a difference signal DEF of each input signal to an output terminal 24c, and this difference signal DEF is applied to the latch circuit 2 at the rising edge of the clamp pulse CP applied to the clamp pulse input terminal 25.
It is latched to 6.

Then, the output of the latch circuit 26 is converted into an analog signal by the D/A converter 27, and applied to the DC level control terminal 22a of the amplifier 22 as the aforementioned control voltage VDC.

With the above configuration, the clamp circuit shown in FIG.
At the rising edge of the clamp pulse CP, a difference signal DEF between the digital signal CL and the A/D converted digital signal VD relating to the target clamp level is latched,
Since the DC level of the amplifier 22 is controlled based on the difference signal DEF, the DC output level of the amplifier 22 can be controlled using the digital signal CL related to the clamp level.

(Problems to be Solved by the Invention) However, although the conventional clamp circuit shown in FIG. 2 has a simple circuit configuration, the temperature characteristics of the voltage source 16 and the A/D converter 14, as well as the power source There is a problem in that fluctuations in the digital output of the A/D converter 14 due to voltage fluctuations and the like overlap, resulting in large fluctuations in the digital output signal VD.

Therefore, for example, when the pedestal level is replaced with a fixed voltage in digital signal processing based on the digital output signal VD, the brightness of the reproduced image may fluctuate.

Furthermore, since the clamp circuit shown in FIG. 3 defines the clamp level using a digital signal, it is possible to eliminate the influence of temperature characteristics in the voltage source 16 shown in FIG. Since the configuration is such that the difference with the signal CL is determined at a specific timing, for example,
If the image signal VI contains noise or the like, an erroneous difference signal DEF may be output, making it impossible to obtain desired characteristics.

Therefore, the noise resistance is improved by sampling the digital output signal VD multiple times over a predetermined period, calculating the average value, and outputting the control voltage VDC based on the calculated average value. However, in this case, a time delay occurs before the control voltage VDC is output, and due to this time delay, desired clamping characteristics may not be obtained.

This invention was made to solve these problems, and its purpose is to eliminate fluctuations in the digital output signal due to the temperature characteristics and power supply voltage characteristics of the A/D converter, and to have excellent noise resistance. Another object of the present invention is to provide a clamp circuit that can control DC component adjustment of an image signal with good followability.

(Means for Solving the Problems) In order to solve the above problems, a clamp circuit according to the present invention includes an amplifier that outputs an image signal whose DC component is adjusted based on a control voltage with respect to an input image signal. , an A/D converter that converts the image signal output from this amplifier into a digital signal, a first D/A converter that converts the conversion output of this A/D converter into an analog signal, and a clamp level. A second method for converting the digital signal related to the analog signal into an analog signal.
a D/A converter, and a sample hold circuit that outputs the analog signal that is the output of the first D/A converter as it is during a period when a clamp pulse is applied, and thereafter holds the value of the analog signal. and a control voltage generation circuit that generates the control voltage based on the difference between the output of the sample and hold circuit and the output of the second D/A converter.

(Function) The image signal whose DC component has been adjusted by the amplifier is
It is converted into a digital signal by a D converter and output. This digital signal is again converted into an analog signal by the first D/A converter. This analog signal is held in a sample and hold circuit based on a clamp pulse. A digital signal related to the clamp level is converted into an analog signal by a second D/A converter. The control voltage generation circuit generates a control voltage based on the difference between the value held by the sample hold circuit and the analog signal that is the output of the second D/A converter,
Based on this control voltage, the DC level of the image signal output from the amplifier is adjusted.

Therefore, based on the digital signal related to the clamp level,
The DC level of the amplifier can be controlled. The sample and hold circuit supplies the analog signal that is the output of the first D/A converter to the control voltage generation circuit during the period when the clamp pulse is applied, so it contains instantaneous noise components. Even in the case of noise, its influence is reduced and noise resistance is improved.

Further, since the control voltage generation circuit is configured to operate by receiving an analog signal as input, there is little time delay in outputting the control voltage, and control with good followability can be performed.

(Example) Embodiments of the present invention will be described below with reference to the accompanying drawings.

FIG. 1 is a block diagram of a clamp circuit according to the present invention.

The image signal VI input to the input terminal 1 is applied to the signal input terminal 2a of the amplifier 2. This amplifier 2 is configured to amplify the signal applied to the signal input terminal 2a and to vary the DC level of the amplified output signal VA based on the control voltage applied to the DC level control terminal 2b. Note that this amplifier 2 may be a buffer circuit with an amplification gain of 1 or an attenuation circuit with an amplification gain smaller than 1.

Amplified output signal VA output to output terminal 2C of amplifier 2
is input to the A/D converter 3, and an A/D converted digital signal VD is output. This output signal VD is the first
The analog signal VADA inputted to the D/A conversion circuit 4 and subjected to D/A conversion by the D/A converter is supplied to the input terminal 5a of the sample hold circuit 5.

The sample hold circuit 5 outputs the signal applied to the input terminal 5a as it is to the output terminal 5C when the control terminal 5b is at the H level, and outputs the signal voltage at the H level when the control terminal 5b is at the L level. It is configured to be retained. The control terminal 5b of the sample and hold circuit 5 is configured to apply the clamp pulse CP input to the clamp pulse input terminal 6. The output terminal 5c of the sample hold circuit 5 is connected to one input terminal 7a of the control voltage generation circuit 7.

The other input terminal 7b of the control voltage generation circuit 7 receives a clamp voltage VCL which is obtained by converting a digital signal CL related to the clamp level into an analog signal via a second D/A converter 8.
is applied.

The control voltage generation circuit 7 is configured to output a DC voltage to the output terminal 7c based on the difference between the signal voltages input to each input terminal 7a and 7b.
For example, it can be configured with a differential amplifier circuit or the like.

The DC voltage outputted to the output terminal 7c is applied to the DC level control terminal 2b of the amplifier 2 as a control voltage VDC.

With the above configuration, during the period when the clamp pulse CP is at H level, if there is a difference between the voltage related to the output signal VA of the amplifier 2 and the clamp voltage specified by the digital signal CL related to the clamp level, The control voltage generation circuit 7 outputs the control voltage VDC to eliminate the difference,
By this control voltage VDC, the amplified output signal V of the amplifier 2 is
The DC level of A is adjusted. The control voltage generation circuit 7 holds the signal voltage when the clamp pulse CP was at the H level during the period when the clamp pulse CP was at the L level.

Therefore, at the output terminal 2C of the amplifier 2, an amplified output signal VA whose DC component is adjusted based on the signal CL related to the clamp level is obtained, and an output obtained by converting this amplified output signal VA into a digital signal VD is obtained. be able to.

(Effects) As explained above, the clamp circuit according to the present invention has
The digital signal obtained by A/D converting the image signal whose DC component has been adjusted is converted into an analog signal again by the first D/A converter, and a digital signal related to this analog signal and the clamp level is generated. and the clamp voltage converted into an analog signal via the second D/A converter are input to the control voltage generation circuit, and the deviation of the DC component is adjusted based on the difference. There is less time delay,
Feedback control with good followability can be performed.

In addition, since the configuration uses a digital signal obtained by A/D converting the output signal of the amplifier as an input signal for feedback control, the digital output is caused by fluctuations in temperature characteristics and power supply voltage of this A/D converter. Including signal fluctuations,
Clamp level adjustment is made.

Furthermore, the sample and hold circuit is configured to continuously supply the analog signal obtained by reconversion to the control voltage generation circuit during the period when the clamp pulse is applied.
Even if the input image signal contains instantaneous noise components, the effect is reduced and noise resistance is improved.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of a clamp circuit according to the present invention, Fig. 2 is a block diagram of a conventional clamp circuit, and Fig. 3 is a block diagram of a clamp circuit according to the present invention.
The figure is a diagram showing the configuration of another conventional boot. 2...Amplifier, 2a...Signal input terminal, 2b...
DC level control terminal, 2C...output terminal, 3...A
/D converter, 4... first D/A converter, 5... sample hold circuit, 7... control voltage generation circuit, 8...
...Second D/A converter, CL...Digital signal related to clamp level, CP...Clamp pulse, ■A...
...Amplified output signal, VADA...analog signal, ■C
L...clamp voltage, VD...digital output signal,
VDC...control voltage, Vl...image signal.

Claims (1)

[Claims] an amplifier that outputs an image signal whose DC component is adjusted based on a control voltage with respect to an input image signal; an A/D converter that converts the image signal output from the amplifier into a digital signal; a first D/A converter that converts the conversion output of the A/D converter into an analog signal; a second D/A converter that converts a digital signal related to the clamp level into an analog signal; A sample and hold circuit outputs the analog signal that is the output of the D/A converter as it is during the period when the clamp pulse is applied and holds the value of the analog signal after that, and the output of this sample and hold circuit and the second A clamp circuit comprising a control voltage generation circuit that generates the control voltage based on a difference between the output of the D/A converter and the output of the D/A converter.