JPH0322917Y2 - - Google Patents
Info
- Publication number
- JPH0322917Y2 JPH0322917Y2 JP1984108343U JP10834384U JPH0322917Y2 JP H0322917 Y2 JPH0322917 Y2 JP H0322917Y2 JP 1984108343 U JP1984108343 U JP 1984108343U JP 10834384 U JP10834384 U JP 10834384U JP H0322917 Y2 JPH0322917 Y2 JP H0322917Y2
- Authority
- JP
- Japan
- Prior art keywords
- hybrid integrated
- integrated circuit
- bridge
- semiconductor element
- circuit board
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/075—Connecting or disconnecting of bond wires
- H10W72/07541—Controlling the environment, e.g. atmosphere composition or temperature
- H10W72/07554—Controlling the environment, e.g. atmosphere composition or temperature changes in dispositions
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/541—Dispositions of bond wires
- H10W72/547—Dispositions of multiple bond wires
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Description
【考案の詳細な説明】
〔考案の技術分野〕
この考案は、混成集積回路基板上の半導体素子
を保護するためのコーテイングを、混成集積回路
基板の一定位置に形成できるようにした混成集積
回路装置に関するものである。[Detailed description of the invention] [Technical field of the invention] This invention is a hybrid integrated circuit device in which a coating for protecting semiconductor elements on the hybrid integrated circuit board can be formed at a fixed position on the hybrid integrated circuit board. It is related to.
従来より混成集積回路において、基板に組み立
てられた半導体素子はその表面保護のために、ジ
ヤンクシヨンコーテイングレジン（以下、JCRと
呼ぶ）により表面塗布されることが多い。第１図
にその一例を示す。
Conventionally, in hybrid integrated circuits, the surface of semiconductor elements assembled on a substrate is often coated with junction coating resin (hereinafter referred to as JCR) in order to protect the surface. An example is shown in FIG.
第１図において、１はセラミツク基板、２は前
記セラミツク基板１上に載置されたマウント台、
３はこのマウント台２上に固着された半導体素
子、４は配線用の金属細線、５は配線用のブリツ
ジ、６はJCRである。 In FIG. 1, 1 is a ceramic substrate, 2 is a mount table placed on the ceramic substrate 1,
3 is a semiconductor element fixed on this mount base 2, 4 is a thin metal wire for wiring, 5 is a bridge for wiring, and 6 is a JCR.
この場合、JCR６を塗布する半導体素子３なら
びにその周辺の形状や、使用するJCR６の性質ま
たは作業時の環境条件により、JCR６の塗布形状
を随意にコントロールすることは極めて困難であ
るため、量産時には幾多のトラブルが発生する。
さらに、回路上に、集積上の向上が強く要求され
るため、このJCR６の塗布後の形状制御は作業性
の向上と合わせて望まれるところである。 In this case, it is extremely difficult to arbitrarily control the shape of the JCR6 applied due to the shape of the semiconductor element 3 to which JCR6 is applied and its surroundings, the properties of the JCR6 used, or the environmental conditions during work. Trouble occurs.
Furthermore, since there is a strong demand for improved circuit integration, it is desirable to control the shape of JCR6 after it is applied, as well as to improve workability.
他の従来例として、第２図に示すようにJCR６
の流れ止め枠（以下バンクと呼ぶ）７を設けた例
もあるが、この場合もバンク７の位置決め固定作
業に問題がある。 As another conventional example, as shown in Figure 2, JCR6
There is an example in which a flow prevention frame (hereinafter referred to as bank) 7 is provided, but in this case as well, there is a problem in positioning and fixing the bank 7.
この考案は、上記の点にかんがみてなされたも
ので、バンク自体の内側にマウント台とブリツジ
の形状に合わせた固定部を設けて、位置決めを容
易にするとともに、量産性に適した混成集積回路
装置を提供することを目的とするものである。以
下、この考案について説明する。
This idea was made in view of the above points, and includes a mounting base and a fixing part that matches the shape of the bridge inside the bank itself to facilitate positioning and to create a hybrid integrated circuit suitable for mass production. The purpose is to provide a device. This idea will be explained below.
第３図ａ，ｂはこの考案の一実施例を示す平面
図およびＡ−Ａ線による断面図である。この図に
おいて、第１図、第２図と同一符号は同一部分を
示し、バンク７をマウント台２とブリツジ５の形
状の一部に係止されるように、バンク７の内側に
固定部８が設けられている。
FIGS. 3a and 3b are a plan view and a sectional view taken along the line A--A of an embodiment of this invention. In this figure, the same reference numerals as in FIGS. 1 and 2 indicate the same parts, and a fixing part 8 is provided inside the bank 7 so that the bank 7 is fixed to a part of the shape of the mount base 2 and the bridge 5. is provided.
以上説明したように、この考案は、JCRの流れ
止め枠の内側にマウント台とブリツジに係止する
固定部を設けることにより、混成集積回路基板の
一定の位置に固定できるように構成したので、混
成集積回路の組立てにおいて半導体素子の表面保
護のために塗布するJCRの塗布作業の作業性の改
善をはかることができるとともに、工程の自動化
が可能となり、集積度の向上をもはかることがで
きる。
As explained above, this invention is configured so that it can be fixed at a fixed position on the hybrid integrated circuit board by providing a fixing part that locks on the mount base and bridge inside the JCR anti-slip frame. It is possible to improve the workability of applying JCR, which is applied to protect the surface of semiconductor elements in the assembly of hybrid integrated circuits, and it also makes it possible to automate the process and improve the degree of integration.
しかも、固定に際しては、混成集積回路基板に
何ら加工を施すことなく、マウント台とブリツジ
を利用して固定できるので、作業がきわめて容易
である効果がある。 Furthermore, when fixing the hybrid integrated circuit board, the mounting table and the bridge can be used to fix the hybrid integrated circuit board without any processing, which makes the work extremely easy.
第１図および第２図は従来の混成集積回路装置
の要部を破断した斜視図、第３図ａ，ｂはこの考
案の一実施例を示す平面図およびＡ−Ａ線による
断面図である。
図中、１はセラミツク基板、２はマウント台、
３は半導体素子、４は金属細線、５はブリツジ、
６はJCR、７はバンク、８は固定部である。な
お、各図中の同一符号は同一または相当部分を示
す。
1 and 2 are perspective views with main parts of a conventional hybrid integrated circuit device cut away, and FIGS. 3a and 3b are a plan view and a sectional view taken along line A-A of this invention. . In the figure, 1 is a ceramic substrate, 2 is a mount stand,
3 is a semiconductor element, 4 is a thin metal wire, 5 is a bridge,
6 is a JCR, 7 is a bank, and 8 is a fixed part. Note that the same reference numerals in each figure indicate the same or corresponding parts.
Claims (1)
に半導体素子が取り付けられ、かつ、配線用のブ
リツジを備えるとともに前記半導体素子を保護す
るためにジヤンクシヨンコーテイングレジンを塗
布する際の前記ジヤンクシヨンコーテイングレジ
ンの流れ止め枠を設けた混成集積回路装置におい
て、前記流れ止め枠の内側に前記マウント台とブ
リツジに係止する固定部を設けたことを特徴とす
る混成集積回路装置。 A semiconductor element is mounted on a mount base placed on a hybrid integrated circuit board, and a bridge for wiring is provided, and the junction coating is applied when a junction coating resin is applied to protect the semiconductor element. What is claimed is: 1. A hybrid integrated circuit device provided with a frame for preventing resin from flowing, characterized in that a fixing portion for locking to the mount base and bridge is provided inside the frame for preventing resin from flowing.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1984108343U JPS6122352U (en) | 1984-07-16 | 1984-07-16 | Hybrid integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1984108343U JPS6122352U (en) | 1984-07-16 | 1984-07-16 | Hybrid integrated circuit device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6122352U JPS6122352U (en) | 1986-02-08 |
| JPH0322917Y2 true JPH0322917Y2 (en) | 1991-05-20 |
Family
ID=30667539
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1984108343U Granted JPS6122352U (en) | 1984-07-16 | 1984-07-16 | Hybrid integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6122352U (en) |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6020929Y2 (en) * | 1980-10-06 | 1985-06-22 | キヤノン株式会社 | Sealing frame structure for electrical circuit elements |
| JPS57170542A (en) * | 1981-04-14 | 1982-10-20 | Seiko Keiyo Kogyo Kk | Semiconductor device |
-
1984
- 1984-07-16 JP JP1984108343U patent/JPS6122352U/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6122352U (en) | 1986-02-08 |
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