JPH03286554A - Multilayer wiring - Google Patents

Multilayer wiring

Info

Publication number
JPH03286554A
JPH03286554A JP8797490A JP8797490A JPH03286554A JP H03286554 A JPH03286554 A JP H03286554A JP 8797490 A JP8797490 A JP 8797490A JP 8797490 A JP8797490 A JP 8797490A JP H03286554 A JPH03286554 A JP H03286554A
Authority
JP
Japan
Prior art keywords
wiring
contact
insulating film
wiring layer
layer wiring
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8797490A
Other languages
Japanese (ja)
Inventor
Seiichi Iwamatsu
誠一 岩松
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP8797490A priority Critical patent/JPH03286554A/en
Publication of JPH03286554A publication Critical patent/JPH03286554A/en
Pending legal-status Critical Current

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 [産業上の利用分野] 本発明は集積回路装置の多層配線法に関し、そのコンタ
クト部構造に関する。
DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to a multilayer wiring method for integrated circuit devices, and to a contact structure thereof.

[従来の技術] 従来、集積回路装置における多層配線のコンタクト部は
第4図で平面図で示した如き構造を取るのが通例であっ
た。すなわち、絶縁体上の第1の下層配線層11はコン
タクト部で線巾を拡大してコンタクト・パッドを形成し
、前記第1の配線層上には絶縁膜が形成され、該絶縁膜
には前記コンタクトパッド部上にコンタクト穴12が形
成されると共に、前記絶縁膜上には第2の上層配線層1
5が前記フンタクト部では線巾を拡大してコンタクト・
パッド部を形成して接続されて成るのが通例であった。
[Prior Art] Conventionally, a contact portion of a multilayer wiring in an integrated circuit device has generally had a structure as shown in a plan view in FIG. That is, the first lower wiring layer 11 on the insulator has a line width expanded at the contact portion to form a contact pad, an insulating film is formed on the first wiring layer, and the insulating film has a A contact hole 12 is formed on the contact pad portion, and a second upper wiring layer 1 is formed on the insulating film.
5 is the contact part by enlarging the line width.
It was customary to connect by forming a pad portion.

[発明が解決しようとする課題] しかし、上記従来技術によるとコンタクト・パッド部を
要する為に、集積回路装置の集積度が向上出来ないと云
う課題があった。
[Problems to be Solved by the Invention] However, the above-mentioned prior art has a problem in that the degree of integration of the integrated circuit device cannot be improved because a contact pad portion is required.

本発明は、かかる従来技術の課題を解決し、集嗜度の向
上を計る事ができる新らしい多層配線法のフンタクト部
構造を提供する事を目的とする。
An object of the present invention is to solve the problems of the prior art and to provide a structure for a new multilayer wiring method that can improve the degree of integration.

[課題を解決するための手段」 上記課題を解決するために、本発明は多層配線法に関し
、絶縁体(絶縁膜及び絶縁基板を含む)上の第一の配線
層と、該第一の配線層上に形成した絶縁膜上の第二の配
線層とを、前記絶縁膜に開けたフンタクト穴を介して接
続するコンタクト部に於て、前記第一の配線層と前記第
二の配線層のいずれにも線巾の拡大によるコンタクト・
バッド部を設けない、いわゆるストレート配線となす手
段を取る。
[Means for Solving the Problems] In order to solve the above problems, the present invention relates to a multilayer wiring method, which includes a first wiring layer on an insulator (including an insulating film and an insulating substrate), and a first wiring layer on an insulator (including an insulating film and an insulating substrate). The first wiring layer and the second wiring layer are connected to the second wiring layer on the insulating film formed on the second wiring layer through a contact hole made in the insulating film. In both cases, contact and
We will use so-called straight wiring without providing a pad.

[実施例] 以下、実施例により本発明を詳述する。[Example] Hereinafter, the present invention will be explained in detail with reference to Examples.

第1図、第2図及び第3図は本発明の実施例を示す多層
配線のコンタクト部の平面図である。
FIGS. 1, 2, and 3 are plan views of contact portions of multilayer interconnections showing embodiments of the present invention.

第1図では、下層配線11上の絶縁膜に開けられたコン
タクト穴12を介して、上層配線13などが接続されて
成る訳であるが、下層配線11及び上層配線13はいず
れもコンタクト部での線巾の拡大によるコンタクト・バ
ッド部は設けず、ストレート配線にて、コンタクト穴1
2が下層配線11の巾よりやや小さく開けられた理想的
な場合の接続方法を示したものである。尚、下層配#1
111及び上層配線13はいずれも絶縁膜上に更に延在
して配線されても良く、又配線方向には特に制限がある
訳でもない。
In FIG. 1, the upper layer wiring 13 and the like are connected through the contact hole 12 made in the insulating film on the lower layer wiring 11, but both the lower layer wiring 11 and the upper layer wiring 13 are connected at the contact portion. No contact pad is provided due to the increased wire width, and contact hole 1 is connected with straight wiring.
2 shows a connection method in an ideal case where the opening is slightly smaller than the width of the lower layer wiring 11. In addition, lower layer #1
Both the wiring 111 and the upper layer wiring 13 may be wired to extend further on the insulating film, and there is no particular restriction on the wiring direction.

第2図では、下層配線11上に該下層配線巾よりやや太
き月に開られたコンタクト穴12を介して上層配線13
を施したものであるが、この場合には、上層配線は、下
層配線11のいずれがの測面ともコンタクト穴部を介し
て接続される。
In FIG. 2, the upper layer wiring 13 is connected to the lower layer wiring 11 through a contact hole 12 that is slightly thicker than the width of the lower layer wiring.
However, in this case, the upper layer wiring is connected to either surface of the lower layer wiring 11 via the contact hole.

第6図では、下層配線11上からややずれた形でコンタ
クト穴12が形成されても上層配線15とは充分に接続
が出来る事を示したものである。
FIG. 6 shows that even if the contact hole 12 is formed slightly offset from above the lower layer wiring 11, it can be sufficiently connected to the upper layer wiring 15.

本発明は、薄膜トランジスタの半導体膜による配線やS
iアゲ−M工S  FETの多結晶S1電極配線等を下
層配線とし、上層配線をAt等の金属配線とした場合に
は特に有効である。
The present invention provides wiring and S
This is particularly effective when the polycrystalline S1 electrode wiring of the iAge-M S FET is used as the lower layer wiring and the upper layer wiring is made of metal wiring such as At.

[発明の効果] 本発明により多層配線の下層配線と上層配線との接続部
にはコンタクト・バッド部として線巾の拡大を要する事
がないので、集積回路装置に応用する場合に、集積度の
向上を計る事ができる効果がある。
[Effects of the Invention] According to the present invention, there is no need to increase the line width as a contact pad portion at the connection portion between the lower layer wiring and the upper layer wiring of the multilayer wiring. It has the effect of being able to measure improvement.

【図面の簡単な説明】[Brief explanation of drawings]

第1図乃至第5図は本発明の実施例を示す多層配線のコ
ンタクト部の平面図であり、第4図は従来技術による多
層配線のコンタクト部の平面図である。 11・・・・・・・・・下層配線 12・・・・・・・・・コンタクト穴 15・・・・・・・・・上層配線 以上
1 to 5 are plan views of a contact portion of a multilayer interconnection according to an embodiment of the present invention, and FIG. 4 is a plan view of a contact portion of a multilayer interconnection according to the prior art. 11...Lower layer wiring 12...Contact hole 15......Upper layer wiring or higher

Claims (1)

【特許請求の範囲】[Claims]  絶縁体上の第一の配線層と、該第一の配線層上に形成
された絶縁膜上の第二の配線層とを、前記絶縁膜に開け
られたコンタクト穴を介して接続するコンタクト部に於
て、前記第一の配線層と前記第二の配線層のいずれも線
巾の拡大によるコンタクト・パッド部を設けない事を特
徴とする多層配線法。
a contact portion that connects a first wiring layer on an insulator and a second wiring layer on an insulating film formed on the first wiring layer through a contact hole formed in the insulating film; A multilayer wiring method characterized in that neither the first wiring layer nor the second wiring layer is provided with a contact pad portion due to an enlarged line width.
JP8797490A 1990-04-02 1990-04-02 Multilayer wiring Pending JPH03286554A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8797490A JPH03286554A (en) 1990-04-02 1990-04-02 Multilayer wiring

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8797490A JPH03286554A (en) 1990-04-02 1990-04-02 Multilayer wiring

Publications (1)

Publication Number Publication Date
JPH03286554A true JPH03286554A (en) 1991-12-17

Family

ID=13929811

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8797490A Pending JPH03286554A (en) 1990-04-02 1990-04-02 Multilayer wiring

Country Status (1)

Country Link
JP (1) JPH03286554A (en)

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