JPH03229455A - Manufacture of capacity element - Google Patents
Manufacture of capacity elementInfo
- Publication number
- JPH03229455A JPH03229455A JP2577190A JP2577190A JPH03229455A JP H03229455 A JPH03229455 A JP H03229455A JP 2577190 A JP2577190 A JP 2577190A JP 2577190 A JP2577190 A JP 2577190A JP H03229455 A JPH03229455 A JP H03229455A
- Authority
- JP
- Japan
- Prior art keywords
- film
- silicon dioxide
- silicon
- reaction tube
- dioxide film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 15
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 87
- 235000012239 silicon dioxide Nutrition 0.000 claims abstract description 44
- 239000000377 silicon dioxide Substances 0.000 claims abstract description 43
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 30
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 29
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 29
- 239000004065 semiconductor Substances 0.000 claims abstract description 28
- 239000000758 substrate Substances 0.000 claims abstract description 27
- 238000006243 chemical reaction Methods 0.000 claims abstract description 26
- 239000007789 gas Substances 0.000 claims abstract description 18
- 230000001590 oxidative effect Effects 0.000 claims abstract description 11
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims abstract description 8
- 239000001301 oxygen Substances 0.000 claims abstract description 8
- 229910052760 oxygen Inorganic materials 0.000 claims abstract description 8
- 238000001947 vapour-phase growth Methods 0.000 claims description 21
- 238000000034 method Methods 0.000 claims description 8
- 239000012535 impurity Substances 0.000 abstract description 5
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 abstract description 4
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 abstract description 3
- MROCJMGDEKINLD-UHFFFAOYSA-N dichlorosilane Chemical compound Cl[SiH2]Cl MROCJMGDEKINLD-UHFFFAOYSA-N 0.000 abstract description 3
- 230000015572 biosynthetic process Effects 0.000 abstract description 2
- 229910052757 nitrogen Inorganic materials 0.000 abstract description 2
- 239000003990 capacitor Substances 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 239000010453 quartz Substances 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000012808 vapor phase Substances 0.000 description 1
Landscapes
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は、絶縁膜を多結晶シリコン膜上に、窒化シリコ
ン膜と二酸化シリコン膜の積層膜を形成した容量素子の
製造方法に間するものである。[Detailed Description of the Invention] Industrial Field of Application The present invention relates to a method for manufacturing a capacitive element in which a laminated film of a silicon nitride film and a silicon dioxide film is formed on a polycrystalline silicon film as an insulating film. .
従来の技術
記憶容量がメガビットクラスの大容量ダイナミックラン
ダムアクセスメモリ（以後、ダイナミックメモリと記す
）では素子数の大容量化にともない半導体記憶素子（以
後、メモリと記す）１個あたりの面積が小さくなってき
た。この結果、メモリセルの容量を確保するために、従
来の基板表面に形成したブレーナキャパシタ（プレーナ
容量素子）にかわり、半導体基板上の大きな段差を利用
した多結晶シリコンを一方の電極とし、この多結晶シリ
コン−ヒに容量絶縁膜を形成するスタックドキャパシタ
が採用されてきている。その容量絶縁膜として窒化シリ
コン膜と二酸化シリコン膜の積層膜を利用する方法が行
われるようになってきた。Conventional technology In large-capacity dynamic random access memory (hereinafter referred to as dynamic memory) with a megabit class storage capacity, the area per semiconductor memory element (hereinafter referred to as memory) has become smaller as the number of elements increases. It's here. As a result, in order to secure the capacity of memory cells, instead of the conventional Brenna capacitor (planar capacitance element) formed on the surface of the substrate, polycrystalline silicon was used as one electrode, making use of the large step difference on the semiconductor substrate. Stacked capacitors in which a capacitive insulating film is formed on polycrystalline silicon have been used. A method of using a laminated film of a silicon nitride film and a silicon dioxide film as the capacitive insulating film has come into use.
以下に、半導体記憶装置等に用いられる従来の記憶素子
の製造方法について第３図に示した断面図を参照して説
明する。以下工程順に説明する。A method of manufacturing a conventional memory element used in semiconductor memory devices and the like will be described below with reference to the cross-sectional view shown in FIG. The steps will be explained below in order.
半導体基板ｌの上に気相成長法により多結晶シリコン膜
２を形成し、この多結晶シリコン膜２に不純物を拡散さ
せることにより導電性を高め、容量素子の一方の電極と
する。この多結晶シリコン膜２の表面は、次の工程であ
る窒化シリコン膜を形成する気相成長装置に投入する際
に気相成長温度の高温の雰囲気にさらされることにより
、２０〜ｌ ００ Ａ Ｎ度酸化され、二酸化シリコン
膜３が形成される。この二酸化シリコン膜３の上に気相
成長により窒化シリコン膜４を形成する。その窒化シリ
コン膜４を酸化炉で一部酸化することにより窒化膜４上
ζこ二酸化シリコン膜５を形成する。A polycrystalline silicon film 2 is formed on a semiconductor substrate l by a vapor phase growth method, and impurities are diffused into this polycrystalline silicon film 2 to improve its conductivity and serve as one electrode of a capacitive element. The surface of this polycrystalline silicon film 2 is exposed to an atmosphere at a high temperature of vapor phase growth temperature when it is introduced into a vapor phase growth apparatus for forming a silicon nitride film in the next step. The silicon dioxide film 3 is then oxidized to form a silicon dioxide film 3. A silicon nitride film 4 is formed on this silicon dioxide film 3 by vapor phase growth. By partially oxidizing the silicon nitride film 4 in an oxidizing furnace, a silicon dioxide film 5 is formed on the nitride film 4.
その上に気相成長により多結晶シリコン膜６を形成し、
この多結晶シリコン膜６に不純物を拡散させることによ
り導電性を高め容量素子の他方の電極とする。以上のよ
うにして多結晶シリコン膜２と６の電極間に二酸化シリ
コン膜３と窒化シリコン膜４と二酸化ノリコンｎｕ ５
の積層容量絶縁膜が形成される。A polycrystalline silicon film 6 is formed thereon by vapor phase growth,
By diffusing impurities into this polycrystalline silicon film 6, its conductivity is increased and it is used as the other electrode of the capacitive element. As described above, the silicon dioxide film 3, the silicon nitride film 4, and the silicon dioxide film nu 5 are formed between the electrodes of the polycrystalline silicon films 2 and 6.
A laminated capacitive insulating film is formed.
発明が解決しようとする課題
しかしながら上記従来の製造方法では、上述したように
窒化シリコン膜４を気相成長させるために気相成長装置
に投入する際に、高温酸化雰囲気中にさらすことにより
多結晶シリコン膜２０表面に二酸化シリコン膜３を形成
するが、窒化シリコン膜４は第３図に示す様な気相成長
装置により形成されるものであり、ヒーター１１により
気相成長温度に加熱された石英製反応管１２に半導体基
板１３が投入される際、複数枚半導体基板支持具１４に
積載されてカンチバトル１５により図面に示した矢印の
方向へ移動していく。従って半導体基板１３のうち移動
方向の前方に位置するへの位置にものと移動方向の後方
に位置するＢの位置にあるものでは、投入が終Ｙして石
英製反応管１２が真空となるまでにヒーター１１から受
して酸化する時間か異なり二酸化シリコン膜３の膜厚が
異なる。このような従来の構成では二酸化シリコン膜３
は、半導体基板内と複数の半導体基板間て大きく膜厚が
異なり、しかも膜厚の制御が困難である。この結果容重
絶縁膜となる積層膜の膜厚もことなるため、メモリセル
容量や電気特性に大きな差が生じるという課題を有して
いた。また窒化シリコン膜４を気相成長させるために気
相成長装置に投入する際の反応管温度を５００℃以下に
すること、もしくは反応管間口部を下に位置するか反応
管前部に予備真空室を設けることによって、多結晶シリ
コン膜２が高温酸化雰囲気中にさらされることがなく表
面に二酸化シリコン膜３が形成することを抑制できるが
、二酸化シリコン膜３が１０Ａ以下の膜厚の場合は積層
容量絶縁膜の電気特性が劣ってしまうという課題を有し
ていた。Problems to be Solved by the Invention However, in the conventional manufacturing method described above, when the silicon nitride film 4 is placed in a vapor phase growth apparatus for vapor phase growth, it is exposed to a high-temperature oxidizing atmosphere to form a polycrystalline film. A silicon dioxide film 3 is formed on the surface of the silicon film 20, and the silicon nitride film 4 is formed using a vapor phase growth apparatus as shown in FIG. When semiconductor substrates 13 are loaded into the manufacturing reaction tube 12, they are loaded onto the semiconductor substrate support 14 and moved by the cantilever battle 15 in the direction of the arrow shown in the drawing. Therefore, among the semiconductor substrates 13, the one located at the front position in the moving direction and the one located at the rear position B in the moving direction, until the loading is finished Y and the quartz reaction tube 12 is evacuated. The thickness of the silicon dioxide film 3 differs depending on the time required for receiving it from the heater 11 and oxidizing it. In such a conventional configuration, the silicon dioxide film 3
The film thickness varies greatly within the semiconductor substrate and between multiple semiconductor substrates, and furthermore, it is difficult to control the film thickness. As a result, the thickness of the laminated film serving as the capacitive insulating film also differs, resulting in a problem of large differences in memory cell capacity and electrical characteristics. In addition, in order to grow the silicon nitride film 4 in a vapor phase, the temperature of the reaction tube should be kept below 500 degrees Celsius when it is introduced into the vapor phase growth apparatus, or the front part of the reaction tube should be placed at the bottom, or the front part of the reaction tube should be placed in a preliminary vacuum. By providing the chamber, the polycrystalline silicon film 2 is not exposed to a high-temperature oxidizing atmosphere, and the formation of the silicon dioxide film 3 on the surface can be suppressed. However, if the silicon dioxide film 3 has a thickness of 10A or less, The problem has been that the electrical properties of the laminated capacitive insulating film are poor.
本発明は、上記従来の課題を解決するもので半導体基板
内と複数の半導体基板間の絶縁膜の膜厚の均一性を向上
させ安定した容量素子を製造する方法を提供することを
目的とするものである。The present invention solves the above-mentioned conventional problems, and aims to provide a method for manufacturing a stable capacitive element by improving the uniformity of the thickness of an insulating film within a semiconductor substrate and between a plurality of semiconductor substrates. It is something.
課題を解決するための手段
本発明の容量素子の製造方法は、半導体基板上に多結晶
シリコン膜を形成し、二酸化シリコン膜及び窒化シリコ
ン膜の形成用ガスを反応管に供給できるようなガス系統
をそなえた気相成長装置の反応管内に前記半導体基板を
投入した後、前記反応管内を酸素を含んだガスで充填す
ることにより、前記多結晶シリコン膜の表面を酸化して
二酸化シリコン膜を形成する工程と、前記反応管内で気
相成長により前記二酸化シリコン膜の表面に窒化シリコ
ン膜を形成する工程と、前記窒化シリコン膜の表面を酸
化して二酸化シリコン膜を形成する工程と、その二酸化
シリコン膜の上に導電膜を形成する工程とを備え、前記
窒化シリコン膜と前記二酸化シリコン膜の積層膜が容量
絶縁膜を形成し、前記多結晶シリコン膜と前記導電膜が
電極を形成するものである。Means for Solving the Problems The capacitive element manufacturing method of the present invention forms a polycrystalline silicon film on a semiconductor substrate, and uses a gas system capable of supplying gas for forming a silicon dioxide film and a silicon nitride film to a reaction tube. After putting the semiconductor substrate into a reaction tube of a vapor phase growth apparatus equipped with the above, the reaction tube is filled with oxygen-containing gas to oxidize the surface of the polycrystalline silicon film to form a silicon dioxide film. a step of forming a silicon nitride film on the surface of the silicon dioxide film by vapor phase growth in the reaction tube; a step of oxidizing the surface of the silicon nitride film to form a silicon dioxide film; forming a conductive film on the film, the laminated film of the silicon nitride film and the silicon dioxide film forms a capacitive insulating film, and the polycrystalline silicon film and the conductive film form an electrode. be.
作用
この製造方法によれは、反応管内に半導体基板を投入し
た後、反応管内に酸素を含んだガスで充填することによ
り多結晶シリコン膜の表面を酸化して二酸化シリコン膜
を形成し、反応管内で気相成長により前記二酸化シリコ
ン膜の表面に窒化シリコン膜を形成するため、多結晶シ
リコン膜と窒化シリコン膜間に二酸化シリコン膜が均一
に形成されるため、膜厚の均一かつ電気特性の良好な積
層容量絶縁膜を形成する。Function: In this manufacturing method, after a semiconductor substrate is placed in a reaction tube, the reaction tube is filled with oxygen-containing gas to oxidize the surface of the polycrystalline silicon film to form a silicon dioxide film. Since a silicon nitride film is formed on the surface of the silicon dioxide film by vapor phase growth, the silicon dioxide film is uniformly formed between the polycrystalline silicon film and the silicon nitride film, resulting in a uniform film thickness and good electrical properties. A laminated capacitive insulating film is formed.
実施例
以下に、本発明の容量素子の製造方法の一実施例を第１
図に示した断面図を参照しながら説明する。第２図は、
同製造方法に使用される装置の略示断面図である。EXAMPLE The following is a first example of the method for manufacturing a capacitive element of the present invention.
This will be explained with reference to the cross-sectional view shown in the figure. Figure 2 shows
FIG. 2 is a schematic cross-sectional view of an apparatus used in the same manufacturing method.
半導体基板２１の上に気相成長により多結晶シリコン膜
２２を形成し、この中に不純物を拡散させて導電性を高
め容量素子の一方の電極とする。A polycrystalline silicon film 22 is formed on a semiconductor substrate 21 by vapor phase growth, and impurities are diffused into this film to increase its conductivity and serve as one electrode of a capacitive element.
次に二酸化シリコン膜と窒化シリコン膜の形成のための
ガス、例えば酸素とジクロルシランガスとアンモニアガ
スを前記反応管３３に供給できるようなガス系統を備え
、かつ大気の巻込みを抑制するために反応管開口部が下
に位置するか、もしくは反応管前部に真空予備室を備え
た気相成長装置に半導体基板２１を投入した後に反応管
３３内に酸素と窒素の混合ガスをながすことにより多結
晶シリコン膜２２の一部を酸化することにより二酸化シ
リコン膜２３を形成上 反応管内を一旦真空排気した後
、ジクロルシランガスとアンモニアガスを導入すること
により気相成長によって二酸化シリコン膜２３上に窒化
シリコン膜２４を形成する。第２図において、３１は半
導体基板支持台具、３１はヒータ、３５は真空バルブ、
３６はメカニカルブースターポンプ、３７はロータリー
ポンプ、３８はガスノズルである。この後この窒化シリ
コン膜２４を酸化炉で酸化することにより二酸化シリコ
ン膜２５を形成し、その上に気相成長により多結晶シリ
コン膜２６を形成し、この膜の中に不純物を拡散させる
ことにより導電性を高め容量素子の一方の電極とする。Next, a gas system capable of supplying gas for forming a silicon dioxide film and a silicon nitride film, such as oxygen, dichlorosilane gas, and ammonia gas, to the reaction tube 33 is provided, and in order to suppress atmospheric entrainment. By flowing a mixed gas of oxygen and nitrogen into the reaction tube 33 after the semiconductor substrate 21 is introduced into a vapor phase growth apparatus in which the reaction tube opening is located at the bottom or a vacuum preliminary chamber is provided at the front of the reaction tube. Forming a silicon dioxide film 23 by oxidizing a part of the polycrystalline silicon film 22 After once evacuating the inside of the reaction tube, dichlorosilane gas and ammonia gas are introduced to form a silicon dioxide film 23 on the silicon dioxide film 23 by vapor phase growth. A silicon nitride film 24 is formed. In FIG. 2, 31 is a semiconductor substrate support fixture, 31 is a heater, 35 is a vacuum valve,
36 is a mechanical booster pump, 37 is a rotary pump, and 38 is a gas nozzle. Thereafter, a silicon dioxide film 25 is formed by oxidizing this silicon nitride film 24 in an oxidation furnace, a polycrystalline silicon film 26 is formed thereon by vapor phase growth, and impurities are diffused into this film. Improves conductivity and serves as one electrode of a capacitive element.
以上のようにして多結晶シリコン膜２２と２６の電極の
間に窒化シリコン膜２４と二酸化シリコン膜２３．２５
の積層容量絶縁膜が形成される。As described above, between the electrodes of the polycrystalline silicon films 22 and 26, the silicon nitride film 24 and the silicon dioxide film 23, 25 are formed.
A laminated capacitive insulating film is formed.
以上のような方法によって、多結晶シリコン膜２２の一
部を酸化することにより形成した二酸化シリコン膜２３
は半導体基板内と複数の半導体基板間ての膜厚の均一性
がすぐれている。従って、半導体基板内と複数の半導体
基板間での積層容量絶縁膜の膜厚が均一化され容量の均
一性が向上するとともに、絶縁膜の経時絶縁膜破壊特性
が改善される。また、上部電極として多結晶シリコン膜
を用いたがシリサイド等の他の導電膜でもよい。Silicon dioxide film 23 formed by oxidizing a part of polycrystalline silicon film 22 by the method described above.
The film thickness uniformity within the semiconductor substrate and between multiple semiconductor substrates is excellent. Therefore, the thickness of the laminated capacitive insulating film within the semiconductor substrate and between the plurality of semiconductor substrates is made uniform, the uniformity of capacitance is improved, and the dielectric breakdown characteristics of the insulating film over time are improved. Further, although a polycrystalline silicon film is used as the upper electrode, other conductive films such as silicide may be used.
また、第１図で示した半導体基板２１の表面は二酸化シ
リコン等の膜で覆われているが、図面及び説明では簡略
化のため省略した。Furthermore, although the surface of the semiconductor substrate 21 shown in FIG. 1 is covered with a film of silicon dioxide or the like, this is omitted in the drawings and description for the sake of brevity.
発明の効果
以上のように本発明の容量素子の製造方法は、多結晶シ
リコン膜上に二酸化シリコン膜と窒化シリコン膜の形成
を行う気相成長装置の反応管内に半導体基板を投入した
後、反応管内に酸素を含んだガスで充填することにより
多結晶シリコン膜の表面を均一に酸化した後、気相成長
により窒化シリコン膜を形成することで、従来より膜厚
が均一になる積層絶縁膜を形成することができる。この
結果、電気特性の均一なすぐれた容量素子が形成され、
これをダイナミックメモリ等に用いることによって信頼
性を向上させることができる。Effects of the Invention As described above, in the method for manufacturing a capacitive element of the present invention, a semiconductor substrate is placed in a reaction tube of a vapor phase growth apparatus that forms a silicon dioxide film and a silicon nitride film on a polycrystalline silicon film, and then a reaction is performed. By filling the tube with oxygen-containing gas to uniformly oxidize the surface of the polycrystalline silicon film and then forming a silicon nitride film by vapor phase growth, we are able to create a laminated insulating film with a more uniform film thickness than before. can be formed. As a result, an excellent capacitive element with uniform electrical characteristics is formed.
Reliability can be improved by using this in a dynamic memory or the like.
第１図は本発明の容量素子の製造方法の一実施例を示す
容量素子の断面図、第２図は同製造方法に使用される装
置の略示断面図、第３図は従来の製造方法により形成さ
れた容量素子の断面図、第４図は従来の窒化シリコン膜
を形成する気相成長装置の断面図である。
２１・・・半導体基板、２２．２６・・・多結晶シリコ
ン膜、２３．２５・・・二酸化シリコン膜、２４・・・
窒化シリコン膜。FIG. 1 is a cross-sectional view of a capacitive element showing an embodiment of the capacitive element manufacturing method of the present invention, FIG. 2 is a schematic cross-sectional view of an apparatus used in the manufacturing method, and FIG. 3 is a conventional manufacturing method. FIG. 4 is a cross-sectional view of a conventional vapor phase growth apparatus for forming a silicon nitride film. 21... Semiconductor substrate, 22.26... Polycrystalline silicon film, 23.25... Silicon dioxide film, 24...
Silicon nitride film.
Claims (1)
コン膜及び窒化シリコン膜の形成用ガスを反応管に供給
できるようなガス系統をそなえた気相成長装置の反応管
内に前記半導体基板を投入した後、前記反応管内を酸素
を含んだガスで充填することにより、前記多結晶シリコ
ン膜の表面を酸化して二酸化シリコン膜を形成する工程
と、前記反応管内で気相成長により前記二酸化シリコン
膜の表面に窒化シリコン膜を形成する工程と、前記窒化
シリコン膜の表面を酸化して二酸化シリコン膜を形成す
る工程と、その二酸化シリコン膜の上に導電膜を形成す
る工程とを備え、前記窒化シリコン膜と前記二酸化シリ
コン膜の積層膜が容量絶縁膜を形成し、前記多結晶シリ
コン膜と前記導電膜が電極を形成することを特徴とする
容量素子の製造方法。A polycrystalline silicon film was formed on a semiconductor substrate, and the semiconductor substrate was placed in a reaction tube of a vapor phase growth apparatus equipped with a gas system capable of supplying gas for forming a silicon dioxide film and a silicon nitride film to the reaction tube. Thereafter, the reaction tube is filled with a gas containing oxygen to oxidize the surface of the polycrystalline silicon film to form a silicon dioxide film, and the silicon dioxide film is formed by vapor phase growth in the reaction tube. a step of forming a silicon nitride film on a surface; a step of oxidizing the surface of the silicon nitride film to form a silicon dioxide film; and a step of forming a conductive film on the silicon dioxide film. A method for manufacturing a capacitive element, characterized in that a laminated film of a film and the silicon dioxide film forms a capacitive insulating film, and the polycrystalline silicon film and the conductive film form an electrode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2577190A JPH03229455A (en) | 1990-02-05 | 1990-02-05 | Manufacture of capacity element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2577190A JPH03229455A (en) | 1990-02-05 | 1990-02-05 | Manufacture of capacity element |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03229455A true JPH03229455A (en) | 1991-10-11 |
Family
ID=12175112
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2577190A Pending JPH03229455A (en) | 1990-02-05 | 1990-02-05 | Manufacture of capacity element |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03229455A (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6049662A (en) * | 1983-08-29 | 1985-03-18 | Nec Corp | Manufacture of semiconductor device |
| JPH021124A (en) * | 1988-06-08 | 1990-01-05 | Sharp Corp | Manufacture of dielectric film |
-
1990
- 1990-02-05 JP JP2577190A patent/JPH03229455A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6049662A (en) * | 1983-08-29 | 1985-03-18 | Nec Corp | Manufacture of semiconductor device |
| JPH021124A (en) * | 1988-06-08 | 1990-01-05 | Sharp Corp | Manufacture of dielectric film |
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