JPH03230227A - Method and device for error detection - Google Patents

Abstract

PURPOSE:To prevent a program from running away by providing a mechanism which monitors the operation of microinstructions through the emulation of the microinstructions by a microprocessor and initiates an interruption when a sequence fault of the microprogram is detected. CONSTITUTION:An microinstruction 5 which is read out of an external memory through a bus control part 4 is decoded by an instruction decoding part 6 to extract a microinstruction 9 and a next-period microinstruction 8 form the microprogram memory and they are sent to a control part 16 and a next-period microinstrument memory storage register 13 in a diagnostic part 11. The microinstruction 9 is sent to a comparing mechanism 14 in the diagnostic part 11 and compared by a comparing mechanism 14 with the next-period microinstruction 8 stored in the next-period microinstruction storage register 13 to diagnose whether or not the microinstruction 9 is an instruction to be executed next. The diagnostic result 12 is sent to an abnormality detecting mechanism 15 in the control part 16 ad if abnormality is detected, an abnormal operation interruption signal 17 is sent out to check its correspondence by an abnormal operation correspondence mechanism 7. Consequently, the program is prevented from running away.

Description

[Detailed Description of the Invention] [Industrial Field of Application] The present invention relates to an error detection method and device, and particularly to an error detection method and apparatus, in particular, on the hardware of a microprocessor. The present invention relates to an error detection method and apparatus for constantly checking operation by comparing code representing a microinstruction to be executed next with a microinstruction to be executed from now on.

[Prior Art] Conventionally, mechanisms for monitoring errors such as runaway programs include mechanisms for monitoring access to illegal address areas that are not supposed to be used during program execution, and mechanisms for checking the data format of instruction execution results. There is a J method.

[Problems to be Solved by the Invention] The conventional mechanism for monitoring illegal accesses in address areas and the mechanism for checking the data type ♂ of the execution result of an instruction cannot be used until the program has progressed to a certain extent after the program has run out of control. It was not possible to detect the moment when the program was about to run out of control.

[Means for Solving the Problems] The error detection method of the present invention adds an operand code section of the next microinstruction to be executed to each microinstruction in advance and stores it in a microprogram memory. Compare the operand code of the next microinstruction to be executed that was attached to the previously executed microinstruction with the operand code of the microinstruction that is about to be executed, and the comparison results do not match. This is a method of generating an interrupt and constantly checking that the microinstruction is about to be executed normally.

The error detection device of the present invention adds the operand food of the next microinstruction to be executed to each microinstruction in advance, and stores the operand food in the microprogram memory and the operand food of the previously executed microinstruction for each execution of the microinstruction. A mechanism that compares the operand code of the next microinstruction to be executed and the operand code of the microinstruction that is about to be executed, which was attached to a microinstruction, and if the comparison results do not match, an interrupt is generated. The present invention is characterized in that it includes a means for generating a microinstruction, and constantly confirms that the microinstruction is about to be executed normally.

C Example Next, the present invention will be explained with reference to the drawings.

FIG. 1 shows a microprocessor to which an error detection method and apparatus according to an embodiment of the present invention is applied.

This microprocessor 22 has an address bus 1. Data bus 2. Bus control signals 3 and a bus control section 4 that controls them. Instruction decoder 8. Instruction execution unit 19. It consists of a control section 169 and a diagnosis section 11, and the instruction decoding section 6 has a microprogram memo υ23.

Next, the operation of this embodiment will be explained according to FIG. 1. The macroinstruction 5 read out from the external memory via the bus control unit 4 is decoded by the instruction decoding unit 6, and the microinstruction 9 and the microinstruction 9 are executed. After that, the next microinstruction 8 to be executed next is taken out from the microprogram memory and sent to the next microinstruction storage register 13 in the control unit 16 and diagnostic unit 11, respectively. The microinstruction 9 sent to the control unit 16 is also sent to the comparison mechanism 14 of the diagnosis unit 11 at the same time, and is compared with the previous next microinstruction 8 stored in the next microinstruction storage register 13 by the comparison mechanism 14. It is diagnosed whether the microinstruction 9 is an instruction to be executed. Diagnosis result 1 compared by comparison mechanism 14
2 is sent to the abnormality detection mechanism 15 in the control section 16, and when an abnormality is detected, an abnormal operation interrupt signal 17 is issued, and the abnormal operation response mechanism 7 takes action. However, when a branch instruction or an interrupt occurs, the next microinstruction to be executed may not be executed. Therefore, when a branch instruction and an interrupt occur, the abnormal operation interrupt signal 17 is masked so that the abnormal operation interrupt signal 17 is not generated even if the microinstruction to be executed next does not match the next microinstruction 8.

Effects of the Invention As explained above, the present invention has a mechanism in which a microprocessor constantly monitors the operation of microinstructions during emulation of microinstructions, and generates an interrupt when an incorrect sequence of the microprogram is detected. ,
This has the effect of preventing programs from running out of control and preventing serious problems such as memory and file destruction.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram of a microprocessor to which an embodiment of the present invention is applied.

1...address bus, 2...data bus, 3...
Bus control signal, 4... Bus control unit, 5... Macro instruction, 6... Instruction decoding unit, 7... Abnormal operation response mechanism,
8...Next microinstruction, 9...Microinstruction, 1
DESCRIPTION OF SYMBOLS 1...Diagnosis unit, 12...Diagnosis result, 13...Next microinstruction storage register, 14...Comparison mechanism, 15
... Abnormality detection mechanism, 16... Control unit, 17... Abnormal operation interrupt signal, 18... Control signal, 19... Instruction execution unit, 20... Address bus, 21... Data bus, 22... microprocessor, 23... microprogram memory.

Claims (1)

[Scope of Claims] 1. The operand code section of the next microinstruction to be executed is added to each microinstruction in advance and stored in the microprogram memory, and each microinstruction is updated with the previously executed microinstruction. The operand code of the microinstruction to be executed next and the operand code of the microinstruction that is about to be executed are compared, and if the comparison results do not match, an interrupt is generated and the microinstruction An error detection method that verifies that an instruction is attempting to execute successfully. 2. The operand code of the next microinstruction to be executed is added to each microinstruction in advance, and the operand code is added to the stored microprogram memory and to the previously executed microinstruction each time the microinstruction is executed. It also includes a mechanism for comparing the operand code section of the microinstruction to be executed next with the operand code of the microinstruction about to be executed, and means for generating an interrupt if the comparison results do not match. An error detection device characterized in that it always confirms that a microinstruction is about to be executed normally.