JPH03230238A - Cache memory control system - Google Patents

Abstract

PURPOSE:To suppress the confliction between cache memory invaridating access and access to the cache memory of this system by invalidating information corresponding to the address of information to be expelled from the cache memory when the information is present on the cache memory. CONSTITUTION:Cache memories 5 - 8 in respective layers are so controlled that pieces of information on cache memories 5 and 6 in an (i)th layer are present on cache memories in (i+1)th layers 7 and 8 without fail. Namely, information which is not present on the cache memories 7 and 8 in the (i+1)th layer is not present on the cache memories 5 and 6 in the (i)th layer. Consequently, when another processor 2(1) sends a cache memory invalidating indication pertaining to store access, the cache memories 5 and 6 in the (i)th layer are informed on ineffective access on condition that information corresponding to an address is stored on the cache memories 7 and 8 in the (i+1)th layer, but not informed if the information is not stored. Consequently, access to a cache memory and cache memory invalidating access never conflict with each other.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a cache memory control method in an information processing device.

[Prior art]

In a tightly coupled multiprocessor in which each processor has its own cache memory, a mechanism is required to ensure information consistency between each cache memory, the main memory, and the cache memory.

In other words, a bus-coupled, tightly coupled multiprocessor in which each processor is connected by a bus monitors the bus to check for memory accesses from other processors, and automatically records information corresponding to the address according to predetermined rules. If the information exists in the cache memory, a method is generally used to ensure that the information matches by invalidating the information. In this case, if the cache memory in the processor has multiple layers, it is checked whether information corresponding to the address is stored in the cache memory of all layers in the processor, and the information is stored. If so, you need to disable it.

FIG. 1 is a block diagram showing a bus-coupled tightly coupled multiprocessor in which each processor individually has two levels of cache memory as described above. In the same figure, 1
, 2 is a processor, 3 and 4 are instruction execution units (hereinafter referred to as CPUs), 5.6 is a first layer cache memory, 7 and 8
9 is a second layer cache memory; 9 is a main memory; 10 is a bus connecting the processors 1, 2 and the main memory 9;
11 and 12 are signal lines connecting the CPUs 3 and 4 to the first layer cache memories 5 and 6, respectively; 13 and 14;
are signal lines connecting the first layer cache memory 5.6 and the second layer cache memory 7.8, respectively.

In the figure, the first layer cache memories 5 and 6 in the processors 1 and 2 have two entries for storing information, and the second layer cache memories 7 and 8 have two entries for storing information.
has four entries. Each entry can hold the address of the stored information in the main memory 9, contents (data), validity/invalidity of the entry, and usage history of each entry (<LRU). It is now assumed that information as shown in FIG. 1 is stored in each entry of the cache memories 5 and 6 of the first layer and the cache memories 7 and 8 of the second layer.

In such a case, the operation of cache memory control will be described below.

First, when the CPU 5 reads information at address 6 of the main memory, the signal ! 11, the address is sent to the first layer cache memory 5. Since the first layer cache memory 5 does not have this information, the address is sent to the second layer cache memory 7 via the signal line 13. Since the second layer cache memory 7 also does not have this information, the bus 1
The contents of address 6 are read from the main memory 9 via 0, and in the cache memory 7 of the second layer, that information is stored in the entry 4 with the largest LRtJ, that is, the entry where the contents of address 0 were previously stored. . Further, the second layer cache memory 7 sends the information to the first layer cache memory 5 via the signal 1a13.

In the cache memory 5 of the first layer, the information is stored in the entry 2 having the largest LRU, that is, the entry in which the contents of address 3 have been stored up to now, and the information is further sent to the CPU 3 via the signal line 11.

A comparison of each entry in the first layer cache memory 5 and the second layer cache memory 7 before and after the CPU 3 reads the information at address 6 of the main memory 9 in this way is shown in FIG. It becomes like this.

[Problem to be solved by the invention]

However, with such control, as can be seen from FIG. 2, there are cases in which the information stored in the first layer cache memory 5 is not stored in the second layer cache memory 7 (in the figure, Address 0 corresponds to this)
. The reason for this is that the LRU of the first layer cache memory 5
is updated by access from the CPU 3, the LRU of the second layer cache memory 7 is updated by access from the first layer cache memory, and the address O with the smallest LRU in the first layer cache memory 5 is the second layer cache memory 7. This is because the LRU of the cache memory 7 becomes the largest.

In this state, when CPU4 performs a store access to rewrite the contents of address 0 from Do to DO+, CPU4
The address and data (Do') sent from is rewritten to DO'. Here, in order to guarantee information consistency in the cache memories, if the contents of address 0 are stored in the cache memory 7 of the second layer and the cache memory 5 of the first layer, the processor 1 must invalidate it. . Therefore, the second layer cache memory 7 of the processor 1 monitors the bus 10, detects a store access from the CPU 4, and first checks whether information at address 0 is stored in the second layer cache memory 7. Check. Since the information at address O is not stored in the second layer cache memory 7 (see (2) in FIG. 2), there is no need to invalidate it. However, as described above, even if the contents of address O do not exist in the cache memory 7 of the second hierarchy, they may exist in the cache memory 5 of the first hierarchy. Therefore, the cache memory 7 in the second layer sends the address to the cache memory 5 in the first layer via the signal line 13, and since the information at address O is stored in the cache memory 5 in the first layer, Disable an entry.

In this way, in conventional cache memory control, because of information matching, when there is a store access from another processor,
Sending the address in the first layer cache memory 5 via the signal line 13 regardless of whether information corresponding to the address exists in the second layer cache memory 7;
It is necessary to check whether information corresponding to the address is stored in the cache memory 5 of the first layer, and if the information is stored, it is necessary to invalidate the information.

Therefore, the CPU's access to its own cache memory and the access for checking its own cache memory accompanying a store access by another processor collide on its own cache memory, resulting in a drawback that the performance of the tightly coupled multiprocessor is degraded.

Therefore, the present invention has been made based on these circumstances, and its purpose is to check the own cache memory associated with the CPU's own cache memory access and the store access of other processors. An object of the present invention is to provide a cache memory control method that greatly reduces collisions between accesses from and on its own cache memory, thereby improving the performance of a tightly coupled multiprocessor.

[Means to solve the problem]

In order to achieve the above object, the present invention basically provides C.
If the information required by the PU does not exist in the cache memory of the first layer, it accesses the cache memory of the second layer, and if it does not exist in the cache memory of the first layer, it accesses the cache memory of the i+1th layer. Finally, if the information required by the CPU does not exist in the cache memory of the Nth hierarchy, in the cache memory of the Nth hierarchy configured to access the main memory, the information required by the CPU does not exist in the cache memory of the first hierarchy. ,
In order to secure an area for storing information required by the CPU, the address of the information to be evicted from the first layer cache memory is determined according to predetermined rules, and the information corresponding to the address is This information is characterized by invalidating the information if it exists in the first layer cache memory.

(2) Furthermore, in a tightly coupled multiprocessor in which a large number of processors each having a cache memory consisting of N layers are connected via a bus as described above, memory accesses of other processors can be detected by the cache memory of the N layer, and predetermined If the information on the cache memory corresponding to the address must be invalidated according to the rules set forth in the table, if the information corresponding to the address does not exist in the cache memory of the Nth layer, no operation is performed, and the information corresponding to the address is invalidated. If exists, the information is invalidated on the cache memory of the Nth layer, and the address is sent to the cache memory of the N-IJ layer, and thereafter, the information corresponding to the address is stored in the cache memory of the first layer in the same way. If the address does not exist, there is no operation, and if the information corresponding to the address exists, the information is invalidated and the i-th
- This is characterized in that the address is sent to the cache memory of the first layer.

[Effect]

The cache memory control method configured in this way is based on the first
The information existing in the cache memory of the hierarchy is always the i+1st
The cache memory of each layer is controlled so that it exists in the cache memory of each layer. This means that information that does not exist in the i+1th layer cache memory is controlled so that it does not exist in the first layer cache memory. Therefore, when cache memory is invalidated due to a store access from another processor, the invalidating access is performed in the first layer only when information corresponding to the address is stored in the cache memory of the i+1th layer. It is possible to notify the cache memory and not to perform the notification when the information is not stored.

Therefore, it is possible to extremely reduce conflicts between accesses to the cache memory from the own CPU and cache memory invalidation accesses accompanying store accesses from other processors.

In this way, it is possible to reduce the frequency of collisions between cache memory accesses from the own CPU and cache memory invalidation accesses associated with store accesses from other processors, thereby improving the performance of tightly coupled multiprocessors. become.

〔Example〕

FIG. 3 is a diagram illustrating an embodiment of the cache control method according to the present invention, and shows the operational flow of the cache memory in response to memory access from the CPU. In the figure, the CPU 3 sends the address of necessary information, and the first layer cache memory 5 determines whether or not the information exists (step 101). If the information exists, the information is read out and sent to the CPU 3 (step 10).
2). On the other hand, if it does not exist, the address of the information required by the CPU 3 is sent to the second layer cache memory 7 (step 103). It is determined whether the information exists (step 104).
). If the information exists, the information is read out and sent to the cache memory 5 of the first layer (
Step 105). In this case, the first layer cache memory 5 stores the information sent from the second layer cache memory 7 and sends it to the CPU 3 (step 106). On the other hand, if the information does not exist, determine the information to be evicted,
The address of the information is stored in the first layer cache memory 5.
The cache memory 5 of the first hierarchy determines whether or not the information to be evicted exists (step 108). If it does not exist, no action is taken (step 109), and if it does exist, the information for planting is invalidated (step 110). In the second layer cache memory 7, after step 107, the address of the information required by the CPU 3 is sent to the main memory 9 (step 111).

The main memory 9 reads out information corresponding to the sent address and sends it to the request source. This information is stored in the second layer cache memory 7 and is also sent to the first layer cache memory 5 (step 112).

Further, FIG. 4 is a diagram for explaining another embodiment of the cache control method according to the present invention, and shows the operation flow of the cache memory in response to invalidation of the cache memory due to store access from another CPU. In the figure, the second layer cache memory 7 monitors main memory accesses from other processors and detects that information corresponding to the address of the access must be invalidated according to predetermined rules. It has become (
Step 201). Then, it is determined whether or not information corresponding to the address exists (step 202). If so, the information is invalidated,
The address is sent to the first layer cache memory 5 (step 203). Note that if it does not exist, it will remain inactive (step 2).
゜4). The first layer cache memory 5 determines whether information corresponding to the address exists (step 205). If it exists, the information is invalidated (step 206). Note that if it does not exist, it will remain inactive (step 2).
07).

Although FIGS. 3 and 4 both show the operational flow of a two-tier cache memory configuration, it goes without saying that a similar configuration can be achieved even in a multi-tier cache memory configuration.

Next, the operation of the cache memory when such a control method is adopted will be explained using FIG.

When the CPU 3 reads information at address 6 of the main memory 9,
The address is sent to the first layer cache memory 5 via the signal line 11. Since the first layer cache memory 5 does not have this information, the address is sent to the second layer cache memory 7 via the signal line 13. Since there is no such information in the cache memory 7 on the second layer, first, in order to secure an area to store the information, the entry with the largest LRU of 4, that is, the entry where the content of address 0 has been stored up until now, is decide. Since the contents of address 0 stored in this entry are invalidated, the address (address 0) is sent to the cache memory 5 of the first layer, and the address is stored in the cache memory 5 of the first layer. If so, instruct to disable it.

Since the first layer cache memory 5 stores the contents of address 0, it is invalidated. Next, in parallel with this, the cache memory 7 of the second layer reads the contents of address 6 from the main memory 9 via the bus 10, and stores it in the entry 4 having the largest LRU. Further, the second layer cache memory 7 sends the information to the first layer cache memory 5 via the signal line 13. In the cache memory of the first layer, the information is stored in the entry 2 with the largest LRU,
That is, the content of address 3 is stored in the entry that has been stored up until now, and the information is sent to the CPU 3 via the signal line 11.
send to

In this way, the first layer cache memory 5 and the second layer cache memory 7 before and after the CPU 3 performs the process of reading out the information at address 6 of the main memory 9.
Each entry is as shown in FIG.

As can be seen from FIG. 5, in the cache memory control according to the above embodiment, when the information stored in the second layer cache memory 7 is to be evicted, the information is stored in the first layer cache memory 5. Since the information is always invalidated, it is guaranteed that information that is not stored in the second layer cache memory 7 is also not stored in the first layer cache memory.

In this state, when CPU4 performs a store access to rewrite the contents of address 0 from Do to DO', CPU4
The address and data (Do') sent from signal line 1
2. The first layer cache memory 6, the signal line 14 and the second
The data is sent to the bus 10 via the hierarchical cache memory 8, and address 0 is rewritten to DO' in the main memory 9.

Here, in order to ensure that the information in the cache memory matches,
In the processor 1, if the contents of address 0 are stored in the second layer cache memory 7 and the first layer cache memory 5, it must be invalidated. Therefore, the second layer cache memory 7 of the processor 1 monitors the bus 10, detects a store access from the CPU 4, and first checks whether information at address 0 is stored in the second layer cache memory 7. Check. Since address 0 is not stored in the second layer cache memory 7, there is no need to invalidate it. Furthermore, in this embodiment, as described above, if the information does not exist in the cache memory 7 of the second layer, it is guaranteed that the information does not exist in the cache memory 5 of the first layer. Therefore, it is no longer necessary for the second layer cache memory 7 to send the address to the first layer cache memory 5 via the signal line 13.

Then, if CPU4 rewrites the contents of address 3,
Since information corresponding to the address exists in the second layer cache memory 7, the information is invalidated and the address is also sent to the first layer cache memory 5. 1st
In the hierarchical cache memory 5, since the information at address 3 is not stored, invalidation processing is not performed.

Furthermore, if CPU4 rewrites the contents of address 6,
Since the second layer cache memory 7 has information corresponding to the address, it invalidates the information and also sends the address to the first layer cache memory 5. In this case, since information at address 6 is stored in the first layer cache memory 5, this information will be invalidated.

As explained above, according to the embodiment described above, when there is cache memory invalidation accompanied by a store access from another processor, the information corresponding to the address is
If it does not exist in the cache memory of the hierarchy, the i-th
There is no need to check the cache memory at the first level or lower, and the frequency with which cache memory accesses from the own CPU collide with accesses for these checks is reduced, which can have the effect of improving the performance of tightly coupled multiprocessors. become able to.

〔Effect of the invention〕

As is clear from the above explanation, according to the cache memory control method according to the present invention, accesses to the own cache memory by the CPU and accesses to check the own cache memory accompanying store accesses by other processors are performed on the own cache memory. Collision on memory can be extremely reduced, thereby improving the performance of tightly coupled multiprocessors.

[Brief explanation of drawings]

Fig. 1 is a block diagram showing the concept of a bus-coupled multiprocessor; Fig. 2 is a diagram showing changes in information stored in the cache memory to explain conventional cache memory control; Fig. 3 and FIG. 4 are diagrams showing the operation flow of a cache memory, which is an embodiment of the cache memory control method according to the present invention. FIG. FIG.

Claims (2)

[Claims] (1) If the information required by the CPU does not exist in the cache memory of the first layer, the cache memory of the second layer is accessed, and if the information does not exist in the cache memory of the i-th layer, the cache memory of the i+1th layer is accessed. When the memory is accessed and the information does not exist in the cache memory of the Nth hierarchy, the information required by the CPU is stored in the cache memory of the ith hierarchy in the cache memory of the Nth hierarchy configured to access the main memory. If it does not exist, in order to secure an area for storing the information required by the CPU, the address of the information to be evicted from the i-th layer cache memory is determined according to predetermined rules, and the information corresponding to the address is 1st floor ~ 1st
A cache memory control method characterized by invalidating information when it exists in a cache memory of a hierarchy. (2) In a tightly coupled multiprocessor in which a large number of processors each having a cache memory consisting of N layers are connected via a bus according to claim 1, the memory accesses of other processors are detected by the cache memory of the N layer, and If the information on the cache memory corresponding to the address must be invalidated according to the rules set forth in the table, if the information corresponding to the address does not exist in the cache memory of the Nth layer, no operation is performed, and the information corresponding to the address is invalidated. If the information exists, the information is invalidated on the cache memory of the Nth layer, and the address is sent to the cache memory of the N-1th layer.
If the information corresponding to the address does not exist in the cache memory of the hierarchy, no operation is performed, and if the information corresponding to the address exists, the information is invalidated and the i-th
A cache memory control method characterized in that the address is sent to a first-layer cache memory.