JPH03230251A - Bus control system - Google Patents

Abstract

PURPOSE:To improve the performance of a system by providing a signal line for all bus control parts connected to a bus, excepting for a bus where a lock signal is turned on, to detect the lock signal, and a signal line to notify it to the bus control part, for which the lock signal is turned on, whether there is write access to a memory or not. CONSTITUTION:Signal lines 102 and 104 are provided to notify whether the output buffer of the bus control part is equipped with the write access to the memory or not, and signal lines 105 and 106 are provided for the bus control parts connected to the buses, excepting for the bus where the lock signal is turned on, to detect the lock signal. For example, when a test & set instruction is executed, a CPU 111 of a processor #1 turns on the lock signal of a bus 101 by a bus control part 107 and a bus control part 114 of a processor #2 detects the ON state through the signal line 105. The bus control part 114 reloads shared data at the first address on a memory 100 and when the write access of the processor #2 is finished, it is notified through the signal line 104 to the bus control part 107 that an output buffer 115 of the bus control part 114 is empty. Thus, the performance of the system is improved.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a bus control system for a multiprocessor in which a plurality of processors and memories are connected by a plurality of buses.

[Prior art]

In a multiprocessor configuration in which a plurality of processors share memory, exclusive control of data shared among the processors is necessary in order to execute processes without contradiction.

Exclusive control is to prevent other processors from using shared data while one processor is processing the shared data.
It consists of two processes (see Figure 2).

Processing ■, test & set instruction (T&S) shared data,
It has a lock byte that indicates whether the data is being processed by the processor. If tt 1 tt is set in the lock byte of some shared data,
This indicates that the shared data is being processed by the processor, and if it is 0'', it indicates that it is not being processed.

The test and set instruction is an instruction for checking whether the processor can use shared data. (1) Read access to the lock byte, (2) Determine whether the read lock byte is set or not. (3) Write access to memory to set the lock byte to “1” if it is On (if it is “1”, another processor has already used the shared data with the corresponding lock byte) (4) Setting a condition code to notify the program whether the lock byte is "O" or "Pa1". While the processor is executing the test & set instruction, the lock signal of the bus connecting the processor and memory is turned on to prevent other processors from accessing the lock byte, and the bus is occupied (locked). ), and prevents other processors from using the bus (Reference: "Nipah Computer Architecture 2nd Edition", Yo Muraoka, Computer Science University Course 11, pp137-139, Kindai Kagakusha).

Process ■, check the condition code to determine whether the shared data can be used, and check if the lock byte is 1.
If it is 1011, process ■, lock byte is “1”
If so, proceed to process ■.

Processing■, Read shared data Read shared data from memory.

Processing ■, roasting process in the processor Processing of the read data by the processor.

Processing (2): Rewriting shared data Write access to write data processed by the processor to memory (hereinafter referred to as STI).

Process ①: Resetting the lock byte Memory write access (hereinafter referred to as ST2) to reset (to "0") the lock byte of the shared data accessed by the processor.

By executing the processes in the above order, processes using shared data can be performed consistently among multiple processors.

One way to improve the unit performance of a processor is to
There is occasional control of write access to memory.

Leave control means that when the instruction execution unit (hereinafter referred to as the CPU) executes a write access, the bus control unit holds the write address and data in an internal output buffer, and transmits the address and data to the CPU. When the CPU receives the instruction, it notifies the end of the write access and prompts the execution of the next instruction, and the writing to the memory is performed in parallel with the execution of the subsequent instruction by the CPU. This control allows the CPU to execute the next instruction without having to wait for the completion of writing to the memory each time a write access is made, thereby improving processing performance.

[Problem to be solved by the invention]

However, in the case of the conventional multiprocessors connected by a plurality of buses, there is a problem in that the above-mentioned exclusive control does not work well when the predetermined control is performed.

This problem will be explained below.

Here, in order to explain the above problem in an easy-to-understand manner,
Assume a multiprocessor configuration in which two processors and one memory are connected by two buses that have a bus locking function (lock signal). Each processor has 1
Consists of one CPU and two bus control units for bus support.
It is assumed that the bus control unit has an output buffer for left-behind control. The shared data is stored at address 1 on the memory, and the lock byte corresponding to the shared data is stored at address 0, and the value of the shared data is assumed to be "A-the value of the lock byte is "0". It is assumed that access to even memory addresses is via bus 0, and access to odd addresses is via bus 1.An overall diagram of the multiprocessor configuration assumed here is shown in FIG.

In FIG. 3, 100 is a memory, #1. #2 is a processor. Processor #1 consists of bus control units 10 and 11 and a CPU 12. Further, processor #2 includes a bus control section 20.21 and a CPU 22.

The bus control section 10 has an output buffer IOA, and the bus control section 11 has an output buffer IIA. Further, the bus control unit 20 has an output buffer 20A, and the bus control unit 20 has an output buffer 20A.
1 has an output buffer 21A.

Next, the operation of each processor #1 and #2 in the multiprocessor configuration described above will be explained.

The CPU 22 of the processor #2 turns on the lock signal of the bus 0, and via the bus control unit 20 and the bus O,
Execute the test & set instruction and set the lock byte at address 0 on memory 100 to "1". Processor #2, which has set the lock byte, turns off the lock signal on bus O.

Obtain access rights to the shared data at address 1 (original data is A).

The CPU 22 of the processor #2 performs read access to the shared data at address 1 on the memory 100 via the bus control unit 21 and the bus 1, and performs processing within the CPU 22.

Next, the CPU 22 of processor #2 writes the processed shared data (new data is B) to address 1 on the memory 100 (STI), so the CPU 22 uses a write address and rewrite data (address is 1. Data is B). ) is sent to the output buffer 21A of the bus control section 21.

The bus control unit 21 stores the STI in the output buffer 21A, and notifies the CPU 22 of the end of the write access.

Subsequently, the CPU 22 of processor #2 uses the memory 100
Reset the mouth at address 0 above (Sr1)
In order to do this, write address and data (address is O,
The data is O) is sent to the bus control unit 20.

The bus control unit 20 stores Sr1 in the output buffer 20A, and notifies the CPU 22 of the end of the write access.

Next, the bus control unit 20 of the processor #2 acquires the bus right to the bus 0, and the S
Send r1 to memory 100 via bus O, and change the lock byte at address 0 on memory 100 from "1" to 3'0.
”. At this time, by chance, bus 1 is being used by processor #1 or an input/output channel (not shown in the figure), bus controller 21 cannot acquire bus 1, and 'sT1 is being used by bus controller 21. 21 remains pending in the output buffer.

This time, the CPU 12 of processor #1 turns on the lock signal of bus 0, executes the test & set instruction via the bus control unit 1o and bus O, and sets the lock byte at address 0 on the memory. is set to “1”. Processor #1, which has set the lock byte, turns off the lock signal of bus 0 and acquires the right to access the shared data at address 1.

At this time, the STI in the output buffer of the bus control unit 21 of processor #2 (address is 1. data is B)
is still on hold.

Next, the CPU 12 of the processor #1 requests the bus control unit 11 to read access to the shared data at address 1 on the memory 100.

Bus control unit 11 attempts to acquire bus 1 for read access to address 1 and bus control unit 21 for write access (STI) to address 1. Although not shown in Figure 1, the bus control unit 21 attempts to acquire bus 1 by using a bus right allocation circuit. Assume that section 11 is given the right to use the bus. The bus control unit 11 reads old data (A) before STI was performed, and reads the old data (A) from the processor #1.
Give to PU12.

Thereafter, processor #1 will continue processing using the old data before being rewritten, resulting in processing inconsistency.

The above-mentioned contradiction occurs in a multiprocessor that includes a plurality of buses and processors that perform left-behind control. For this reason, conventional methods for configuring a multiprocessor include a method in which no output buffer is provided in the bus control unit and control of write access is not performed in advance, or a method in which only one bus is used.

The former method prevents processing inconsistency by not allowing the next memory access (S T 2) to be executed until the memory write access (STl) is executed on the memory and completed. However, as explained in the first half of this article, there was a problem in that the performance of the processor alone was not improved because it did not perform left-behind control.

In the latter method, by using one bus, write access STI and Sr1 to the memory are serialized on the bus, and Sr1 does not overtake STI and is reflected in the memory, so the above-mentioned problem does not occur. However, this method has a problem in that bus contention increases as the number of processors increases, resulting in saturation of processing performance.

The present invention has been made to solve the above problems.

SUMMARY OF THE INVENTION An object of the present invention is to provide a bus control method suitable for a multiprocessor that has a plurality of buses and is configured of processors that perform selective control.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means to solve the problem]

In order to achieve the above object, the bus control method of the present invention includes:
Multiple processors with output buffers that enable effective left-handed control of write access to memory and memory are connected to multiple buses with lock signals for exclusive control of memory access from multiple processors. In a combined multiprocessor configuration, if the CPU of a predetermined processor issues a read access with the lock signal turned on via a predetermined bus control unit and bus, the CPU of a predetermined processor is connected to a bus other than the predetermined bus of another processor. All bus controllers detect this lock signal and indicate that the output buffer is empty when there is no write access to memory in the output buffer, while indicating that the output buffer is empty when there is a write access to memory in the output buffer. , after performing the write access to the memory, notifies the bus control unit that issued the read access with the lock signal turned on that the output buffer is empty, and the bus control unit The most important feature is that the data read from the memory is sent to the CPU after receiving the notification from all the bus control units connected to the bus other than the bus.

[Effect]

According to the above-mentioned means, when a predetermined CPU issues a read access with a lock signal turned on via a predetermined bus control unit and bus, all bus control units connected to other processors other than the predetermined bus detects the lock signal,
When there is no write access to memory in the output buffer, the output buffer is empty; on the other hand, when there is a write access to memory in the output buffer, after performing the write access to memory, The bus control unit that issued the read access with the lock signal turned on is notified that the output buffer is empty, and the bus control unit receives notification from all bus control units connected to other processors other than the predetermined bus. After receiving the notification, the data read from memory is sent to the CPU, so it has multiple buses.
Furthermore, it is possible to realize a bus control method suitable for a multiprocessor configured of processors that perform left-behind control.

In other words, the bus control method of the present invention is different from the conventional technology as follows.
All bus control units connected to the bus other than the one on which the lock signal is turned on use the lock signal to detect whether or not there is a write access to memory on the signal line for detecting the lock signal and the output buffer of the bus control unit. The difference is that it has a signal line for notifying the bus control unit that the bus has been turned on.

[Embodiments of the invention]

Hereinafter, one embodiment of the present invention will be specifically described using the drawings.

FIG. 1 is a block diagram showing the configuration of a multiprocessor for explaining a bus control method according to an embodiment in which the present invention is applied to a multiprocessor that has a plurality of buses and is composed of processors that perform leftover control. It is a diagram.

In FIG. 1, 100 is a memory having shared data and a lock byte indicating whether or not the data is accessed;
101.103 is a bus, 102.104 is a signal line that notifies whether the output buffer of the bus control unit has write access to memory, and 105.106 is connected to a bus other than the bus with the lock signal turned on. Signal line for the bus control unit to detect the lock signal, 107.109.11
2.114 is a bus control unit for controlling access to the memory 100, 108.110.113° 115 is an output buffer of the bus control unit necessary for performing leftover control, and 111.116 is a CPU that executes instructions. (instruction execution unit).

When the bus control method of the present invention is applied, two types of newly added signal lines (102, 104, 105
, 106), the overall block configuration is assumed to be exactly the same as the multiprocessor configuration shown in FIG.

Next, the operation of each processor in the multiprocessor configuration will be explained.

The CPU 116 of the processor #2 turns on the lock signal of the bus O, executes the test & set instruction via the bus control unit 112 and the bus 101, and sets the lock byte at address 0 on the memory to 1''. Processor #2, which has set the lock byte, turns off the lock signal on bus 101 and acquires the right to access the shared data at address 1 (original data is A).

The cp U116 of the processor #2 is the bus control unit 11
4. Read access is made to the shared data at address 1 on the memory 100 via the bus 103, and the CPU 1
Processing is performed within 16.

Next, the CPU 116 of processor #2 writes the processed shared data (the new data is B) to the area at address 1 on the memory 100 (STI), so the CPU 116 of processor #2 writes the write address and the rewrite data (the address is 1° and the data is B) is sent to the bus control unit 114.

The bus control unit 114 stores the STI in the output buffer 115 and notifies the CPU 116 of the end of the write access.

Subsequently, the C:PU 116 of processor #2
In order to reset the lock byte at address 0 on 00 (Sr1), the write address and data (address is O, data is 0) are sent to the bus control unit 112.

The bus control unit 112 stores Sr1 in the output buffer 113 and notifies the CPU 116 of the end of the write access.

Next, the bus control unit 112 of processor #2 acquires the bus right to bus 0 and uses Sr1 stored in the output buffer.
is sent to the memory 100 via the bus 101, and the lock byte at address 0 is reset from "1" to II OIT. At this time, bus 103 happened to be connected to processor #1.
Or, although not shown in the figure, the bus 103 is used by the input/output control channel, the bus control unit 114 cannot acquire the bus 103, and the STI is used by the output buffer 11 of the bus control unit 114.
5 remains pending.

FIG. 1 illustrates the multiprocessor in the state described above.

Assuming that the multiprocessor is in the state shown in FIG. 1, CP Ull of processor #1 issues a read request for the lock byte at address 0 on memory 100 to bus control unit 107 in order to execute a test & set instruction. Bus control section 1
07 acquires the bus right to the bus 101, turns on the lock signal of the bus 101, and issues a read request for address O on the memory 100.

At this time, the bus control unit 114 of processor #2
It is detected through the signal line 105 that the lock signal 01 is in the on state.

In response to this detection, the bus control unit 114 sends a write address and data (STI near address is 1, data is B) to rewrite the shared data held in the output buffer 115 via the bus 103. Send to memo official month 00 and rewrite the shared data at address 1 on memo January 00 from "A" to "B IT".

When the write access by processor #2 is completed, the output buffer 115 of the bus control unit 114 is empty, so the bus control unit 114 reports this to the bus control unit 107 via the signal line 104.

After reading the lock byte from the memory 100, the bus control unit 107 of processor #1 sends the above report to the CPU
Send to lll. Since the lock byte is O, CP Ull acquires the access right to the shared data and sends a write access to set the lock byte to 1 to the bus control unit 107. The bus control unit 107 stores the write access in the output buffer 108 and notifies the CPU Ull of the end of the write access.

Next, CP Ull moves on to reading the shared data, but at this time, the shared data has been rewritten to 'B', and henceforth processing is performed without any contradiction.

The present invention has been specifically explained above based on examples, but
It goes without saying that the present invention is not limited to the embodiments described above, and can be modified in various ways without departing from the spirit thereof.

〔Effect of the invention〕

As described above, according to the present invention, it is possible to adopt a multiprocessor configuration in which processors that perform leftover write control are connected via a plurality of buses, and the performance of the system can be improved.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of a multiprocessor for explaining a bus control system according to an embodiment in which the present invention is applied to a multiprocessor that has a plurality of buses and is composed of processors that perform leftover control. FIG. 2 is an operation flowchart of exclusive control of write access to memory performed by a processor, and FIG. 3 is a diagram for explaining the operation of a conventional multiprocessor having a plurality of buses. In the figure, 100, memory, 101, 103, bus, 1
02.104...Signal line, 105.106...Signal line, 107.109.112゜114...Bus control unit, 108.110.113.115...Output buffer, 111.116...・CPU.

Claims (1)

[Claims] (1) Multiple processors and memories are connected by multiple buses, and each processor is composed of an instruction execution unit and multiple bus control units provided corresponding to the buses to control access to the memory. Memory access from the execution unit is performed via an address, which is uniquely determined according to predetermined rules, and each bus receives a lock signal for exclusive control of memory access from multiple processors. The bus control unit has an output buffer and outputs addresses and data in response to write access from the instruction execution unit. In a multiprocessor bus control system configured to notify the instruction execution unit of the end of write access when stored in the buffer, and send the write address and data to the memory when the bus is acquired, a predetermined instruction is executed. When a processor issues a read access with a lock signal turned on via a predetermined bus controller and bus, all bus controllers connected to other processors other than the predetermined bus detect the lock signal, When there is no write access to memory in the output buffer, the output buffer is empty; on the other hand, when there is a write access to memory in the output buffer, after the write access to memory is performed, The bus control unit that issued the read access with the lock signal turned on is notified that the output buffer is empty, and the bus control unit receives notification from all bus control units connected to other processors other than the predetermined bus. A bus control method characterized in that after receiving the notification, data read from memory is sent to an instruction execution unit.