JPH03230393A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To simplify address decoding and to make access efficient by constituting a label field in a semiconductor storage part. CONSTITUTION:The semiconductor storage part 16 shared by data processors 1 to 3 are divided into areas based on a device label, a command label and a parameter label set up in a label field 27. In the case of accessing the storage part 16 from the processors 1 to 3 through respective access address buses 5, 7, 9, an address bus 11 and an address bus 13 of an address decoder 14 for the storage part 16, the storage part 16 can be selected by a small address bit width. Consequently, the access can be rapidly and efficiently executed. When substorage bits 40, 41 are constituted in the storage bit 17 of the storage part 16, different processing can be executed by the access based on the same address.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a semiconductor memory device in a data processing device.

2. Description of the Related Art Conventionally, as shown in FIG. 2, a semiconductor memory device shared by a plurality of data processing devices is connected to a bus together with the plurality of data processing devices, and data is stored using an address issued by the data processing device. was selected. That is, in FIG. 2, the first to third data processing devices 1.2
．． 3 to the respective address bus 5.7.9 and bus 11
The semiconductor storage unit 16 was accessed via the address bus 13 to the address decoder 14 of the semiconductor storage unit 16. However, when the first data processing device 1 executes the instructions stored in the semiconductor storage unit 16 and controls the other second and third data processing devices 2.3,
Among the number of accesses to the semiconductor storage unit 16, the number of accesses by the first data processing device 1 accounts for most of the number of accesses, and the disadvantage is that the time required for access via the bus 11 becomes longer. Moreover, since the entire address space of the semiconductor storage section 16 is shared by each data processing device 1, 2.3, there is a drawback that the time required for decoding an address becomes longer. Similarly, since all commands and parameters are accessed only by address, there is a drawback that decoding takes a long time. Furthermore, when each data processing device 1.2.3 uses different parameters in the same command and performs unlinked processing, there is a drawback that access must be executed again after accessing the command.

On the other hand, as another conventional example, as shown in FIG.
．． 20, but in this system, each data processing device 1, 2.3 has a semiconductor memory section 18, 19, .
20, and a considerable amount of time is required to make it unique.

Problems to be Solved by the Invention An object of the present invention is to eliminate the above-mentioned conventional drawbacks and provide a semiconductor memory device having an efficient access method.

Means for Solving the Problems In order to achieve this object, in the present invention, a label field, a sub-storage bit, and an output port dedicated to each data processing device are configured in the semiconductor storage section.

Effect: With this configuration, address decoding can be simplified, different parameters can be simultaneously accessed with the same command, and moreover, efficient access can be achieved without requiring a semiconductor memory section unique to each data processing device.

Example An embodiment of the present invention will be described based on FIG.

In FIG. 1, 1, 2.3 are data processing devices fi, 5,
7, 9.13 are access address buses, 11 is an address bus, 36.37, 38.39 are access label buses,
35 is a label bus, 32゜33.34 is an access data bus, 29, 30゜31 is an output port, 27 is a label field, 14 is an address decoder, 15.28 is a signal line, 16 is a semiconductor storage section, 17 is a memory bit, 40.4
1 is a sub storage bit.

The semiconductor storage unit 16 shared by the first to third data processing devices 1, 2.3 is divided into areas according to the device label, command label, and parameter label set in the label field 27. .3, when the semiconductor memory section 16 is accessed via the respective access address buses 5, 7.9, the address bus 11, and the address bus 13 of the address decoder 14 of the semiconductor memory section 16, a smaller address bit width is selected. Therefore, high-speed access is possible. In addition, the data processing device 1
, 2.3, and the access data bus 32.33.34, it is possible to simultaneously issue commands and parameters to each data processing device. . Furthermore, storage bit 1 of a certain address in the semiconductor storage unit 16
By configuring sub-storage bits 40.41 to 7,
It becomes possible to execute different processes by accessing the same address.

DETAILED DESCRIPTION OF THE INVENTION As described in the detailed description of the invention, the present invention achieves extremely high efficiency by accessing storage bits and sub-storage bits of a semiconductor storage section from a plurality of data processing devices via a label field, an address decoder, and a dedicated output port. It has the effect of being easily accessible and improving operability.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, and FIG. 2 is a block diagram of an example of a conventional data processing system.
FIG. 3 is a block diagram of a conventional example of a data processing system in which each data processing device has its own semiconductor memory section. 1.2.3...Data processing device, 4,6,8゜12.21,23.25...Access data bus, 10...Data bus, 5, 7,9,13,
22゜24.26...Access address bus,
11...address bus, 14...address decoder, 15°28...signal line, 16,
18, 19.20... Semiconductor storage section, 17...
...Storage bit, 40.41 ...Sub storage bit, 27 ...Label field, 36.3
7, 38, 39...Access label bus, 35
・・・・・・Label bus, 29.30.31・・・・・・
- Output port, 32, 33, 34...Access data bus.

Claims (5)

[Claims] (1) A semiconductor memory device characterized in that it has a semiconductor memory section that is accessed by a plurality of data processing devices, a label field is configured in the semiconductor memory section, and each of the plurality of data processing devices is accessed. 2. The semiconductor storage device according to claim 1, wherein the label field is utilized for each storage element of the semiconductor storage section and accessed for each command and parameter. (3) The semiconductor memory device according to claim 1, wherein each bit of the semiconductor memory section is configured with a sub-storage bit so that multiple processes can be performed at the same address. (4) The semiconductor memory device according to claim 1, further comprising an output port that is accessible to a plurality of data processing devices. (5) The semiconductor according to claim 1, wherein the system has an output port compatible with a plurality of data processing devices, and each bit of the semiconductor storage section has a sub-storage bit for each data processing device. Storage device.