JPH03230394A - Random access memory - Google Patents

Abstract

PURPOSE:To compare the data of two RAMs with each other by means of short wirings and a data bus by arranging plural repeated units each of which two RAMs are combined on a substrate and drawing out their bit lines. CONSTITUTION:Two RAMs having the equal number of bits in each word and the equal number of words to be stored are integrally constituted on the substrate. When an address 1 for accessing the 1st RAM is decoded by a decoder 21 and a reading voltage is impressed to a word line W1, data are outputted to respective bit lines of the 1st RAM and respectively sent to a comparator 4. When an address 2 for accessing the 2nd RAM is decoded by a decoder 22 and a reading voltage is impressed to a word line W2, data are outputted to the bit lines of the 2nd RAM and respectively sent to the comparator 4. The comparator 4 compares the outputs of the bit lines Bm1, Bm2 with each other to discriminate coincidence/discrepancy. Consequently, the data of two RAMs can be compared by means of the short wirings and the data bus.

Description

[Detailed Description of the Invention] :Summary: Regarding a RAM having a configuration suitable for comparing data stored in RAM, two RAMs each store data by wiring and a data bus. The object of the present invention is to form a repeating unit by combining bit cells constituting the first RAM and bit cells constituting the second RAM. A plurality of these repeating units are arranged on a substrate to constitute one RAM, and data of each bit of the first and second R and AM is transmitted from each of the two types of bit lines belonging to one of the repeating units. It was configured to obtain.

[Industrial application field]

The present invention relates to a RAM in which two RAMs are integrated and has a configuration suitable for comparing data stored in random access memory (hereinafter referred to as RAM).

[Conventional technology]

An example of a conventional basic configuration for comparing data stored in two RAMs is shown in FIG. 2(a).
The #1 address for reading data from #lRAM11+ is decoded by the decoder 12, and the #lRAM1
1□, the data stored in this #1 address is read bit by bit via the read/write circuit 13, and is supplied to one input terminal of the comparator 10.

Similarly, the #2 address is decoded by the decoder 122 to access this 92RAM 112, and the data stored in the #2 address is read out bit by bit via the read/write circuit 132, and the data is sent to the other input terminal of the comparator 10. to perform a bitwise comparison.

However, in this conventional method, #
It is necessary to wire conductors corresponding to the respective bits from IRAM11l and #2RAM11□ to each input terminal of the comparator 10, which not only requires time and effort, but is also undesirable due to the capacitance caused by this wiring. ) could have an impact.

In order to eliminate such drawbacks, two RAMs 21. ．． 21° symmetrically arranged,
From the above RAM21+, the #1 address is decoded to the decoder 22.
The output of each bit line decoded and accessed and read by 1 is transferred to one input terminal of the comparator 20 disposed between these two RAM21+ and '212, and the output from the RAM21□ is The output of each bit line read in the same manner by the #2 address is transferred to the other input terminal of the comparator 20, and the comparator 20 outputs R,
There is one that compares data stored in 4M2 I+, 212.

However, in such a configuration, RAM21.
．． In order to write/read data to/from 21□, a read/write circuit provided in each RAM is used. ．． 2
3□, which caused a problem in that the data bus 24 for transferring data became long.

σ Problems to be Solved by the Invention 2 The present invention is designed to solve two R,
The purpose of this invention is to construct a RAM that can compare the data stored in A and M.

[Means to solve the problem]

As shown in (C) of the principle embodiment of FIG. 1, a repeating unit is formed by combining bit cells constituting the first RAM and bit cells constituting the second RAM, A plurality of RAMs are arranged on a substrate to form one RAM, and the data of each bit of the first and second RAMs is obtained from each of two types of bit lines belonging to one of the repeating units. did.

By forming the first RAM and the second RAM on the same substrate and drawing out their bit lines,
Since the comparator can be provided adjacent to this RAM, the conductor from the bit line to the comparator can be shortened, and at the same time the length of the data bus can be shortened.

Embodiment] Figure 1 quoted above shows a principle embodiment of the present IJ in which two RAMs with the same number of bits per word and the same number of words that can be stored are configured as a single unit. ,
Figure (b) is an enlarged view of a portion of Figure (a), showing a total of six repeating units arranged in two rows and three columns, and Figure (C) is a portion of Figure (b) above. is further expanded to illustrate one repeating unit.

In this figure (C), the bit cell CI indicated by the line downward to the left belongs to the first RAM, and the bit cell C2 indicated by the line downward to the right belongs to the second RAM.
M! ::It is the cell to which it belongs.

# for accessing the first RAM shown in FIG.
1 address to decoder 2. As a result of decoding, when a reading voltage is applied to the word line WI, as illustrated for the m-th pinpoint belonging to this word,
Data of "O" or "1" of each bit is outputted to each bit line and sent to the comparator 4 provided at an adjacent position, similarly to the illustrated focus line Bffil.

On the other hand, as a result of decoding the #2 address for accessing the second RAM by the decoder 22, the word line W2
For example, when a read voltage is applied to the m-th bit belonging to this word, as shown in the example for the m-th bit belonging to this word, the data of each bit (0 or 1) is transferred to the bit line B shown in the example.
Two. Similarly to the above, the signals are output to each bit line and sent to the comparators 4 provided at adjacent positions.

In this embodiment, since the number of bits in one word is the same in the first R48 and in the second RAM, the comparator 4 compares the outputs of the bit lines Bffil and B, 2. A match or mismatch of the data of the mth bit can be identified.

In addition, if the number of words and/or number of bits that can be stored in the first RAM and the second RA~1 differs by q, the common multiple of the ratio of the number of words in these two RAMs and 2 Similarly, the upper part can be constructed by using a common multiple of the ratio of the number of bits of two RAMs as the vertical and horizontal number of bit cells in one repetition unit.

〔Effect of the invention〕

According to the present invention, not only can the data stored in two RAMs be compared using short wiring, but also the data stored in two RAMs can be compared.
A special effect is achieved in that the data bus for writing/reading these RAMs can also be shortened.

[Brief explanation of drawings]

FIG. 1 is a diagram showing a principle embodiment of the present invention, and FIG. 2 is a diagram showing a conventional comparison method. (a) Conventional example diagram read/write chain-9 (b)

Claims (1)

[Claims] forming a repeating unit in which bit cells constituting the first RAM and bit cells constituting the second RAM are combined;
By arranging a plurality of these repeating units on a board, one RAM is created.
and belongs to one of these repeating units.
A random access memory characterized in that the data of each bit of the first and second RAMs is obtained from each of the different bit lines.