JPH03230609A - Digital filter - Google Patents

Abstract

PURPOSE:To halve number of multipliers with respect to a tap number by employing a same type of multiplier for an i-th tap multiplier and an (m-i+1)th tap multiplier. CONSTITUTION:The filter consists of (m-1)/2 sets of adders 21 summing signals of i-th tap (i=1,2,..., (m-1)/2) (m is an odd number) and a signal of (m-i+1)th tap, (m-1)/2 sets of multipliers 13 receiving outputs of the adders and multiplying a prescribed tap number with the signals, a multiplier 13 receiving a signal of an (m+1)/2 tap and multiplying a prescribed tap coefficient with the signal and an adder 15 summing outputs of each multiplier. Thus, a same multiplier is used for the i-th tap multiplier 13 and the (m-i+1)th tap multiplier. Thus, number of the multipliers in use is halved with respect to the tap number.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a digital filter used as a roll-off filter for waveform shaping. In particular, the present invention relates to a transversal filter that is an acyclic (FIR) digital filter that can ideally achieve linear phase characteristics.

[Prior Art] FIG. 6 is a block diagram showing a configuration example of a conventional transpersal filter.

In the figure, the transpersal filter includes a delay circuit 11. ~1 time, and the input signal (x(t-2)) and the output (x(t-1), ..., ), a (-1), ..., a (+2) )
Multiplier 13. ~t3s and adders 151 to 154 that add the outputs of the respective multipliers (tap outputs),
This is a configuration that obtains a filter output.

Note that a transposed type transversal filter shown in FIG. 7 has also been devised, and the same operation is performed.

In other words, the input signal is divided into five branches, each with a predetermined tap coefficient (a(-2), a(-1),..., a(+2)).
), and sequentially delays and adds each multiplier output (tap output) to obtain a filter output.Those with the same numbers as in Figure 6 perform the same functions. .

By the way, in actual circuits, there are those with analog configuration and those with digital configuration, but recent LSI
With the development of technology, digital filters in which all three basic components (delay circuit, multiplier, adder) are implemented with digital elements have been put into practical use.

In such a digital filter, the frequency characteristics of the input and output signals are G (f) and F (f
), the n-stage tap coefficients can be found as follows. That is, the tap coefficient is a value obtained by sampling the impulse response of the desired frequency characteristic divided by the frequency characteristic of the input signal (filter transfer frequency F (f)/G (f)).

Here, if the output signal of the digital filter for the input signal x(t) at time t is y(t), the output signal y(t) is delayed by n time slots with respect to the input signal x(t), and y( t) - Σ a (i) ・x (t - i)
・"The value determined by (2) is output. Note that the number of taps is 2n+1.

On the other hand, the accuracy of a digital filter depends on the finite number of taps, and to realize a highly accurate digital filter, it is necessary to increase the number of taps as much as possible.

[Problem to be solved by the invention]

However, in the conventional configuration, one multiplier is required for each tap, and when the number of multipliers, which make up most of the circuit configuration of a digital filter, increases as the number of taps increases, the circuit scale becomes significantly large. was.

An object of the present invention is to provide a digital filter that can halve the number of multipliers relative to the number of taps.

[Means for Solving the Problems] The digital filter of the present invention as set forth in claim 1 includes m-1 delay circuits that give a predetermined delay to an input signal and branch into m (m is an odd number) tap signals. In an m-order acyclic digital filter, which has a configuration in which tap outputs obtained by multiplying each tap by a predetermined tap coefficient are added, the i-th tap (i=1.2, ..., (m-1) /2) and the signal of the m-i+1 tap are added (m-1)/
Two adders, (m-1)/2 multipliers that take the adder output as input and multiply each by a predetermined tap coefficient, and take the signal of the (m+1)/2th tap as input and multiply it by a predetermined tap coefficient. The multiplier is configured to include one multiplier that multiplies tap coefficients of , and an adder that adds the outputs of each multiplier.

The digital filter of the present invention according to claim 2 has m-1 delay circuits that give a predetermined delay to an input signal and branch into signals of m (m is an even number) taps, and each tap has a predetermined delay. In an m-th acyclic digital filter that is configured to add tap outputs multiplied by tap coefficients, the signal of the i-th tap (i = 1.2, ..., m/2) and the m-th
m/2 adders that add the i+1 tap signals;
It is configured to include m/2 multipliers that take the adder output as input and multiply each multiplier by a predetermined tap coefficient, and an adder that adds the outputs of each multiplier.

The digital filter of the present invention as set forth in claim 3 branches an input signal, and sequentially delays and adds tap outputs obtained by multiplying each tap by a predetermined tap coefficient.
In an m-th order acyclic digital filter having 1 (an odd number) delay circuits and adders, the input signal is
m + 1) / 2 tap signals, the i-th tap (i = 1.2, ... (m-1) / 2) signal is multiplied by a predetermined tap coefficient, and the i-th tap and (m-1)/2 multipliers that output two branches as the tap output of the m-i+i tap, and a multiplier that multiplies the signal of the (m+1)/2 tap by a predetermined tap coefficient,
/2 tap output.

The digital filter of the present invention as set forth in claim 4 branches an input signal, and sequentially delays and adds tap outputs obtained by multiplying each tap by a predetermined tap coefficient.
In an m-order acyclic digital filter having 1 (an even number) delay circuits and adders, the input signal is
/2 tap signal, and the i-th tap (i=1.2,
. . , m/2) by a predetermined tap coefficient, and outputs two branched outputs as tap outputs of the i-th tap and the m-i+1-th tap.

[For production]

The i-th tap multiplier and m−i+1
The principle by which tap multipliers can be shared will be explained. In addition, in the following explanation including the examples, for convenience, the
m+1)/2 tap is the O-th tap, and the -i-th tap is
This will be explained as a tap multiplier and a +i-th tap multiplier.

For example, when shaping the rectangular pulse G (f) into a cosine roll-off waveform F (f), where the time width τ, the roll-off rate α, and the Nyquist frequency f0 are as follows: (4).

Here, the impulse responses of G (f) and F (f) are both even functions that are symmetrical about 1=0, as shown in FIG. Note that the horizontal axis is time, and To(=
1/2fo) is the Nyquist interval. Also, Figure 2 (
2) is ω. It is normalized by /π.

Therefore, the desired frequency characteristic (F (f)) divided by the frequency characteristic (G (f)) of the input signal (F (f
)/G(f)) is also an even function, and the tap coefficients found as values obtained by sampling it are symmetrical as shown in FIG. Note that in FIG. 3, black dots indicate sampling points, that is, tap coefficients.

On the other hand, the tap coefficient of the transversal filter is (1)
It can be found from the formula, but the value is symmetrical as described above.

That is, a(-i)=a(+i)...(
5), the multiplier of the −i-th tap and the multiplier of the i-th tap can be made the same. Note that the filter output y(t) is obtained by substituting the equation (5) into the equation (2), y(t
)−a(0)・x(t) (6)

The digital filter according to claims 1 to 4 includes an i-th tap multiplier and an m-i-th tap multiplier according to the inventive principle explained above.
This shows a configuration for sharing a +1 tap multiplier.

〔Example〕

Hereinafter, embodiments of the present invention will be described in detail based on the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of the digital filter of the present invention.

In the figure, the feature of the present invention is that the i-th tap multiplier and the m-i+l-th tap multiplier can be shared, so the 5-tap multiplier corresponding to the conventional configuration shown in FIG. In this embodiment showing a transversal filter, a multiplier (1
3+, 13s), tap coefficient a (-1), a(+
1) The multipliers (13z, 134) for multiplying by 1) are made common to each other.

That is, delay circuits (shift registers) 111 to 114
gives a predetermined delay to the input signal, and x(t-2) to x(t
+2) signal is generated. Adder 21. adds the input signal x(t-2), which is the signal of the i-th tap, and the output x(t+2) of the delay circuit 114, which is the signal of the fifth tap, and sends the result to the multiplier LL. The adder 212 outputs the output x(t-1) of the delay circuit 11+, which is the second tap signal, and the output x(t+1) of the delay circuit 11, which is the fourth tap signal.
) are added and sent to the multiplier 13□.

Multipliers t3+ to 133 are connected to each adder 21. ．． Output of 21□ x(t-2) +x(t+2), x(t-1) +x
(t+1) and the delay circuit 11 which is the third tap signal
The output x(t) of g is input and multiplied by predetermined tap coefficients a(2), a(1), and a(0), respectively. Adder 15
1.152 adds each multiplier output (tap output).

Here, the outputs of each multiplier are a(2) ・(x(t-2) +x(t+2)), a(
1) ・(x(t-1) +x(t+1)), a (0
)・x(t), and the output signal y<t> of the digital filter obtained by adding them becomes y(t)=a(0)・x(t) (7).

Further, the present invention can be similarly applied to the transposed type transversal filter shown in FIG. 7, and an example of its configuration is shown in FIG.

Note that in this embodiment as well, a multiplier 131 that multiplies the conventional configuration (5 taps) of the transposed transversal filter shown in FIG. 7 by tap coefficients a(-2) and a(+2) is used. .13. and tap coefficient a (-1)
, a (+1), respectively, can be shared.

That is, the output of the multiplier 131 is branched and sent to the delay circuit 11. as the i-th tap signal and the fifth tap signal. and the adder 154, and the output of the multiplier 13□ is branched to the adder 15. and sends it to the adder 153. Note that the output of the multiplier 133 is sent to the adder 152 as a third tap signal.

By the way, the embodiment configuration shown above has an odd number of taps (5
), but if the number of taps is even, there is simply no tap coefficient a(0) that is the center of symmetry, so the present invention can be applied in the same way.

FIG. 5 is a block diagram showing a configuration example of a transversal filter having four taps.

In the figure, adder 31. is the i-th tap signal, input signal x(t-2), and the output x(t+1) of the delay circuit 113, which is the fourth tap signal, is added to the multiplier 13.
The adder 31□ adds the output x(t-1) of the delay circuit 111, which is the second tap signal, and the output x(t) of the delay circuit 11z, which is the third tap signal. It is sent to the multiplier 13□.

Multiplier 13. ．． 13□ indicates each adder 31. ．． 312 output x(t-2) +x(t+1), x(t-1) +x
(t), respectively predetermined tap coefficients a(2),
Multiply by a(1). The adder 151 receives each multiplier output (
tap output) to obtain the output signal.

Note that when the number of taps is an even number, the same applies to a transposed transversal filter.

〔Effect of the invention〕

As described above, the present invention can approximately halve the number of multipliers relative to the number of taps. Therefore, even when the number of taps is increased as accuracy is improved, the number of multipliers that occupy most of the circuit configuration in the digital filter can be reduced, and the overall circuit scale can be significantly reduced.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the digital filter of the present invention. FIG. 2 is a diagram showing the impulse responses of C, (f) and F (f). FIG. 3 is a diagram showing that the tap coefficients are symmetrical. FIG. 4 is a block diagram showing the configuration of a transposed type transversal filter according to an embodiment of the present invention. FIG. 5 is a block diagram showing the configuration of an embodiment of the present invention of a transversal filter having an even number of taps. FIG. 6 is a block diagram showing an example of the configuration of a conventional transversal filter. FIG. 7 is a block diagram showing a configuration example of a conventional transposed type transversal filter. FIG. 8 is a diagram showing frequency characteristics of input and output signals of a digital filter. 11... Delay circuit, 13... Multiplier, 15... Adder, 21.31... Adder. (1) (2) (1) (2) (1) (2)

Claims (4)

[Claims] (1) Has m-1 delay circuits that give a predetermined delay to the input signal and branch into m (m is an odd number) tap signals, and add the tap outputs obtained by multiplying each tap by a predetermined tap coefficient. In an m-th order acyclic digital filter that has a configuration of (m-1)
/2 adders; (m-1)/2 multipliers that take the adder output as input and multiply each by a predetermined tap coefficient; and (m+1)-th multiplier.
1. A digital filter comprising: one multiplier that receives a /2 tap signal and multiplies it by a predetermined tap coefficient; and an adder that adds the outputs of each of the multipliers. (2) Has m-1 delay circuits that give a predetermined delay to the input signal and branch into m (m is an even number) tap signals, and add the tap outputs obtained by multiplying each tap by a predetermined tap coefficient. In an m-th order acyclic digital filter, the signal of the i-th tap (i=1, 2,..., m/2) and
m/2 adders that add the signals of −i+1 taps, m/2 multipliers that take the adder output as input and multiply each by a predetermined tap coefficient, and add the outputs of each of the multipliers. 1. A digital filter comprising: an adder. (3) m-order having m-1 (m is an odd number) delay circuits and adders that sequentially delay and add the tap output obtained by branching the input signal and multiplying each tap by a predetermined tap coefficient; In the acyclic digital filter, the input signal is split into (m+1)/2 tap signals, and the i-th
The signals of the taps (i=1, 2, ..., (m-1)/2) are each multiplied by a predetermined tap coefficient, and the signals are output in two branches as the tap outputs of the i-th tap and the m-i+1-th tap (
m-1)/2 multipliers, and one multiplier that multiplies the signal of the (m+1)/2 tap by a predetermined tap coefficient and outputs it as a tap output of the (m+1)/2 tap. A digital filter characterized by: (4) m-order having m-1 (m is an even number) delay circuits and adders that sequentially delay and add the tap output obtained by branching the input signal and multiplying each tap by a predetermined tap coefficient. In the acyclic digital filter, the input signal is branched into m/2 tap signals, and the i-th tap (i=1, 2,..., m/2) signal is multiplied by a predetermined tap coefficient, i-th tap and m-th tap
m/2 to output 2 branches as tap output of i+1 tap
A digital filter characterized by comprising a multiplier.