JPH03230650A - Afc circuit - Google Patents

Abstract

PURPOSE:To make a frequency of an IF signal inputted to a demodulation circuit stable by counting a frequency of a carrier recovered directly and comparing the frequency with a reference frequency so as to apply fine adjustment of a reference oscillator. CONSTITUTION:A frequency division ratio of a variable frequency divider 110 of a PLL circuit 5 is set to sweep an oscillating frequency of a reference oscillator 6. When a carrier recovered by a carrier recovery circuit 9 synchronizes with a frequency of an intermediate frequency signal (IF signal), the sweep of the reference oscillator 6 is stopped to count the frequency of the carrier recovered directly and the frequency is compared with a reference frequency to apply fine adjustment to the oscillated frequency of the reference oscillator 6. Thus, the frequency of an IF signal inputted to a demodulation circuit 8 is made stable and the frequency of the IF signal is matched with the regular frequency more accurately.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an AFC circuit, and more particularly to an AFC circuit that stabilizes the frequency of a frequency-converted digital modulation signal input to a demodulation circuit.

[Prior Art] Generally, when demodulating a digital modulation signal, an AFC circuit is used to stabilize the frequency of the signal input to the demodulation circuit. FIG. 5 is a schematic block diagram showing an example of such a conventional AFC circuit. First, the configuration of the conventional AFC circuit 103 will be explained with reference to FIG. The frequency conversion circuit 100 converts the frequency of the input digital modulation signal, outputs an intermediate frequency signal (hereinafter referred to as an IF multiplied signal), and supplies the signal to the demodulation circuit 101 . Recap circuit 1
01 demodulates the digital modulation signal output from the frequency conversion circuit 100. The demodulation circuit 101 includes a carrier wave regeneration circuit 102 for regenerating a carrier wave.

The AFC circuit 103 is provided to stabilize the IF multiplied signal frequency output from the frequency conversion circuit 100, and includes a frequency divider 104, a counter 105, and a microprocessor 10.
6 and a PLL circuit 107. The frequency divider 104 divides the frequency of the IF multiplied signal, and the counter 105 divides the frequency of the frequency divider 10.
Count the IF multiplied signal frequency divided by 4. Based on the count output of the counter 105, the microprocessor 106 controls the variable branching unit 11 included in the PLL circuit 107.
Controls 0.

The PLL circuit 107 includes a voltage controlled oscillator (VCO) 108, a prescaler 109, a variable frequency divider 110, and a reference oscillator 1.
11, a phase comparator 112, and a loop filter 113. Voltage controlled oscillator 108 is microprocessor 106
The oscillation frequency changes according to a control signal given from the local oscillation circuit 10.
0 and the prescaler 109. Prescaler 10
Reference numeral 9 divides the frequency of the local oscillation signal by a pre-fixed frequency division ratio, and supplies the divided output to the variable division divider 110 .

The variable frequency divider 110 divides the local oscillation signal frequency-divided by the prescaler 109 by a frequency division ratio set by the microprocessor 106. The frequency-divided output of variable frequency divider 110 is provided to phase comparator 112 . Phase comparator 11
2 compares the phase of the local oscillation signal frequency-divided by the variable divider 110 and the frequency of the reference signal output from the reference oscillator 111, and outputs an error signal. The error signal is given to the loop filter 113 and smoothed, giving vC010
8 as a control voltage.

Next, the operation of the conventional AFC circuit 103 shown in FIG. 5 will be explained. When the microprocessor 106 sets the pre-stored frequency division ratio to the variable division divider 110, V
C0108 converts the corresponding local oscillation signal into frequency conversion circuit 1
Output to 00. The digital modulation signal input to the frequency conversion circuit 100 is converted into an IF signal. The microprocessor 106 divides this IF multiplied signal frequency into the frequency divider 104.
Then, the counter 105 is controlled so that the counter 105 counts for a certain period of time, and the count output counted by the counter 105 is taken in. The microprocessor 106 compares the captured count output with the reference value of the IF multiplied signal reference signal stored in advance in the microprocessor 106, calculates an error amount from the comparison result, and adjusts the variable division according to the error amount. The frequency division ratio of the carrier 110 is adjusted to stabilize the carrier wave output from the carrier wave regeneration circuit 102 so that it falls within a range in which it is synchronized with the IF multiplied signal frequency.

[Problems to be Solved by the Invention] In the conventional AFC circuit 103 shown in FIG.
Therefore, if the C/N decreases, the frequency divider 104, which divides the frequency of the IF multiplied signal, will not operate normally and a counting error will occur. Therefore, the IF multiplied signal may be detuned from the normal frequency, the demodulation characteristics may deteriorate, and furthermore, the carrier wave may become out of synchronization with the IF multiplied signal frequency. In addition, since the IF multiplied signal is stabilized by changing the frequency division ratio of the variable frequency divider 110, the step of the oscillation frequency of VC0108 increases,
Since the IF multiplied signal frequency always deviates greatly from the normal frequency, there is a drawback that it adversely affects the demodulation characteristics.

Therefore, the main object of the present invention is to provide an AFC circuit that can accurately stabilize the IF multiplied signal frequency even when the C/N is low and can reduce the IF multiplied signal frequency shift.

[Means for Solving the Problems] The present invention includes a frequency conversion circuit that converts the frequency of a digital modulation signal and outputs an intermediate frequency signal, and a demodulation circuit that reproduces a carrier wave of the intermediate frequency signal and synchronizes the carrier wave. AF that is connected to the carrier regeneration circuit that outputs the detection signal and stabilizes the frequency of the intermediate frequency signal that is input to the demodulation circuit.
C circuit, a counting means for counting the frequency of the carrier wave regenerated by the carrier wave regeneration circuit, and a voltage controlled oscillation means for providing the frequency conversion circuit with a local oscillation signal whose oscillation frequency changes according to the input voltage. The frequency division ratio is made variable,
A variable frequency dividing means for frequency dividing a local oscillation signal generated from the voltage controlled oscillation means, a reference oscillation means whose oscillation frequency is varied by voltage control and generates a reference signal, and a divided output of the variable frequency dividing means. A phase comparison means that compares the phase with a reference signal generated from the reference oscillation means and varies the oscillation frequency of the voltage controlled oscillation means according to the comparison result, and voltage data for determining the oscillation frequency in the reference oscillation means. At the same time, the division ratio data for determining the frequency division ratio is set in the division means, and the voltage data given to the reference oscillation means is swept until the synchronization detection signal is given from the carrier wave regeneration circuit. Depending on what is given,
The control means compares the count output of the counting means with a predetermined reference value, and finely adjusts the voltage data applied to the reference oscillation means so that the comparison output falls within a predetermined range.

[Function] In the AFC circuit according to the present invention, the control means sets voltage data for determining the oscillation frequency in the reference oscillation means, and sets frequency division ratio data for determining the frequency division ratio in the division means. , the digital modulation signal input to the frequency conversion circuit is subjected to IF times signal frequency conversion. Next, the control means sweeps the voltage data applied to the reference oscillation means while referring to the synchronization detection signal output from the carrier wave regeneration circuit, and a synchronization detection signal indicating that the carrier wave is synchronized with the IF multiplied signal frequency is provided. , the sweep is stopped, and the carrier waves are counted by the counting means for a certain period of time. The control means compares this counted value with a predetermined reference value, and if the counted value exceeds the permissible range, finely adjusts the voltage data given to the reference oscillation means so that the counted value falls within the permissible range. Thereby,
The frequency can be counted accurately even when the C/N is low, and the IF multiplied signal frequency can be stabilized.

Further, since the reference frequency of the reference oscillation means of the PLL circuit can be finely adjusted by changing it, the IF multiplied signal frequency can be more accurately matched to the regular frequency.

[Embodiment of the Invention] FIG. 1 is a schematic block diagram showing an embodiment of the invention. Since the AFC circuit shown in this embodiment is the same as the conventional AFC circuit shown in FIG. 5 except for the following points, only the different configurations will be described. The reference oscillator 6 included in the PLL circuit 5 is one whose oscillation frequency can be controlled according to an external voltage. The control voltage for the reference oscillator 6 is given by converting digital voltage data output from the microprocessor 2 into an analog signal by the D/A converter 7. In addition, the demodulation circuit 8
The carrier regeneration circuit 9 included in the microprocessor 2 not only outputs the regenerated carrier signal to the branching unit 3 but also
A synchronization detection signal indicating that the carrier wave is synchronized with the IF multiplied signal frequency is output.

The counter 4 counts the frequency-divided output by the frequency divider 3 and provides the counted output to the microprocessor 2.

FIG. 2 is a flowchart for explaining the operation of one embodiment of the present invention, and FIG. 3 is a diagram showing an example of the voltage versus frequency characteristic of the reference oscillator.

Next, with reference to FIGS. 1 to 3, a specific operation of an embodiment of the present invention will be described.

First, the microprocessor 2 outputs to the D/A converter 7 an initial value for determining the oscillation frequency of the reference oscillator 6 of the PLL circuit 5. This data is converted into an analog signal by the D/A converter 7 and set in the reference oscillator 6 as a voltage value. Next, the microprocessor 2 sets pre-stored frequency division ratio data to the variable frequency divider 110.

Then, the PLL circuit 5 performs a predetermined PLL operation, and v
A predetermined local oscillation signal is output from the cO 108, and a digital modulation signal input to the frequency conversion circuit 100 is converted to an IF signal.
The signal frequency is converted twice. The microprocessor 2 refers to the synchronization detection signal output from the carrier wave regeneration circuit 9 and determines whether the carrier wave is synchronized with the IF times signal frequency. if,
When the carrier wave is not synchronized with the IF times signal frequency,
D/A to sweep the reference frequency of the reference oscillator 6
The data output to the converter 7 is adjusted. For example, if the sweep waveform is a silver wave and the voltage vs. frequency characteristic 10 of the reference oscillator 6 is as shown in FIG. Assuming that the value and the maximum value are Nm1n and Nmax, respectively, a loop may be set in which the minimum value is increased to the maximum value as Nm1n-*Nmax, and then returns to the minimum value again. Also, if you want the sweep waveform to be a triangular wave, you can do the same by creating a loop that decreases from the largest value to the smallest value and repeats this.

The microprocessor 2 determines the synchronization detection signal output from the carrier wave regeneration circuit 9, and repeats sweeping the reference oscillator 6 in a step manner so that the carrier wave is
When synchronization with the double signal frequency is detected, the reference oscillator 6 is taken out of the sweeping loop and moved to a loop that counts the frequency of the carrier wave.

In this loop, first, the regenerated carrier wave output from the carrier wave regeneration circuit 9 is fixedly divided by the frequency divider 3,
A counter 4 counts the frequency-divided carrier waves for a certain period of time. The microprocessor 2 takes in the counting output of the counter 4 and compares it with a pre-stored reference value. If a tolerance value that does not affect the demodulation characteristics of the demodulation circuit 8 is set as a reference value, if the count value is within the tolerance range, the frequency of controlling the reference oscillator 6 will be reduced, and the step-like drift of the IF multiplied signal will be reduced. can be reduced, and the demodulation characteristics can be improved.

Now, when the count value is within the allowable range, there is no need to change the oscillation frequency of the reference oscillator 6, and when the count value is smaller than the lower limit of the allowable value, the D/A increases the oscillation frequency of the reference oscillator 6. It is sufficient to increase the data output to the converter 7, and conversely decrease the data when the value is larger than the upper limit of the allowable value. After this, the microprocessor 2 again determines whether the carrier wave is synchronized with the IF multiplied signal frequency. If it is synchronized, it returns to the loop that counts the frequency of the carrier wave, and if it is not synchronized, it moves to another loop. When setting the division ratio and reference frequency data in such an operation, it is possible to proceed to the next operation after the frequency has stabilized, and it is also possible to move to the next operation after the frequency is stabilized. If it is not synchronized with the double signal frequency, it is also possible to sweep the oscillation frequency of the reference oscillator 6 again by adjusting the frequency division ratio of the variable frequency divider 110.

As described above, according to this embodiment, the frequency division ratio of the variable frequency divider 110 of the PLL circuit 5 is set, the oscillation frequency of the reference oscillator 6 is swept, and the carrier wave regenerated by the carrier wave regeneration circuit 9 is converted into an IF multiplied signal. When synchronized with the frequency, the sweep of the reference oscillator 6 is stopped, the frequency of the directly reproduced carrier wave is counted, and the oscillation frequency of the reference oscillator 6 is finely adjusted.
The IF multiplied signal frequency input to the demodulation circuit 8 can be stabilized. Therefore, it is possible to accurately count frequencies even when the C/N is low, and it is possible to stabilize the IF multiplied signal frequency input to the demodulation circuit 8, making it possible to more accurately match the IF multiplied signal frequency to the regular frequency. be able to.

FIG. 4 is a diagram showing an example of the reference oscillator shown in FIG.
O) 11 and a frequency divider 12,
FIG. 4(b) shows a device constructed by a voltage controlled oscillator (VCO) 13 and a frequency divider 12. In Figure 1, the frequency fluctuation of the digital modulation signal is small, ±0.01%.
VCXOII can be used as the reference oscillator 6 if the frequency fluctuation becomes large, but if the frequency fluctuation becomes large, it is necessary to use a VC013 using a SAW resonator, ceramic resonator, etc. that can have a wide variable range.

[Effects of the Invention] As described above, according to the present invention, the frequency division ratio of the variable frequency division means is set, the oscillation frequency of the voltage-controllable reference oscillation means is swept, and the carrier wave built in the demodulation circuit is When the carrier wave of the reproduction circuit is synchronized with the IF multiplied signal frequency, the sweep of the reference oscillation means is stopped, the frequency of the directly reproduced carrier wave is counted, and the control means compares it with the reference value to finely adjust the oscillation frequency of the reference oscillation means. By doing this, the IF of the frequency-converted digital modulation signal input to the demodulation circuit is
Double signal frequency can be stabilized. Therefore, even when the C/N is low, frequencies can be counted accurately, the IF multiplied signal frequency input to the demodulation circuit can be stabilized, and the IF multiplied signal frequency can be more accurately matched to the regular frequency.

[Brief explanation of drawings]

FIG. 1 is a schematic block diagram of an embodiment of the present invention. FIG. 2 is a flow diagram for explaining the operation of one embodiment of the present invention. FIG. 3 is a diagram showing an example of voltage versus frequency characteristics of a reference oscillator. FIG. 4 is a diagram showing an example of the reference oscillator shown in FIG. 1. FIG. 5 is a schematic block diagram showing a conventional AFC circuit. In the figure, 1 is an AFC circuit, 2 is a microprocessor, 3 is a frequency divider, 4 is a counter, 5 is a PLL circuit, 6 is a reference oscillator, 7 is a D/A converter, 8 is a demodulation circuit, and 9 is a carrier wave regeneration The circuit includes a frequency conversion circuit 100, a voltage controlled oscillator 108, a prescaler 109, a variable frequency divider 110, a phase comparator 112, and a loop filter 113.

Claims (1)

[Claims] Included in a frequency conversion circuit that converts the frequency of a digital modulation signal and outputs an intermediate frequency signal, and a demodulation circuit, regenerates a carrier wave of the intermediate frequency signal and outputs a synchronization detection signal of the carrier wave. an AFC circuit connected to a carrier wave regeneration circuit to stabilize the frequency of an intermediate frequency signal input to the demodulation circuit, and counting means for counting the frequency of the carrier wave regenerated by the carrier wave regeneration circuit; Voltage controlled oscillation means for providing the frequency conversion circuit with a local oscillation signal whose oscillation frequency changes according to the voltage; and a variable frequency division ratio thereof that divides the frequency of the local oscillation signal generated from the voltage controlled oscillation means. a frequency dividing means, a reference oscillation means whose oscillation frequency is varied by voltage control and generates a reference signal, a phase of a frequency divided output of the variable frequency dividing means and a reference signal generated from the reference oscillation means is compared; , phase comparison means for varying the oscillation frequency of the voltage controlled oscillation means according to the comparison result, and voltage data for determining the oscillation frequency set in the reference oscillation means, and a frequency division ratio set in the frequency division means. setting frequency division ratio data for determining, sweeping the voltage data applied to the reference oscillation means until a synchronization detection signal is provided from the carrier wave regeneration circuit, and in response to the application of the synchronization detection signal, An AFC circuit comprising: a control means for comparing the count output of the counting means with a predetermined reference value and finely adjusting voltage data applied to the reference oscillation means so that the comparison output falls within a predetermined range.