JPH03236226A - Manufacturing method of semiconductor device - Google Patents
Manufacturing method of semiconductor deviceInfo
- Publication number
- JPH03236226A JPH03236226A JP3352590A JP3352590A JPH03236226A JP H03236226 A JPH03236226 A JP H03236226A JP 3352590 A JP3352590 A JP 3352590A JP 3352590 A JP3352590 A JP 3352590A JP H03236226 A JPH03236226 A JP H03236226A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- manufacturing
- silicon
- contact
- forming
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Thin Film Transistor (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
[産業上の利用分野]
本発明は半導体装置の製造方法に関し、より詳しくはオ
ーミック性のコンタクト部を有する半導体装置の製造方
法に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a semiconductor device having an ohmic contact portion.
[従来の技術]
従来の半導体装置製造においては、特に半導体材料であ
るシリコンやポリシリコンに対する電気的な接触部(コ
ンタクト部)の形成は、歩留り、信頼性、半導体特性等
を決定する重要な工程である。シリコン上に金属層を形
成させると両者の間に仕事関数差に基づき接触電位差が
生じる。−船釣に配線電極として使用されるAIの仕事
関数値はシリコンに比べて仕事関数が負でオーミック性
の接合となる。[Prior Art] In conventional semiconductor device manufacturing, the formation of electrical contacts, especially for semiconductor materials such as silicon and polysilicon, is an important process that determines yield, reliability, semiconductor characteristics, etc. It is. When a metal layer is formed on silicon, a contact potential difference occurs between the two based on the difference in work function. -The work function of AI used as wiring electrodes for boat fishing is negative compared to silicon, resulting in an ohmic junction.
しかし、シリコン表面に常に薄い酸化膜(50〜100
人)が形成されているため、実際にはA1を単にシリコ
ンと接触させるだけではオーミック特性は得られない。However, the silicon surface always has a thin oxide film (50 to 100
In reality, simply bringing A1 into contact with silicon does not provide ohmic characteristics.
この問題を解決する方法として特開昭60−1869号
公報では電極配線形成前に長時間高温水素熱処理を行い
、電極配線形成後に短時間熱処理する方法が提案されて
いる。すなわち、この方法では、第2図に示すように多
結晶シリコンの堆積[第2図(b) ] 、パターン形
成[第2図(C) ] 、ゲート絶縁膜3の積層[第2
図(d)]、ゲート4の形成・イオン5の打ち込み[第
2図(e) ] 、眉間絶縁膜6の形成・長時間の高温
水素熱処理[第2図(f) ] 、コンタクトホール8
の形成・Al電極lOの形成[第2図(g)]の各工程
を経て電極形成が行われる。As a method for solving this problem, JP-A-60-1869 proposes a method in which a long-time high-temperature hydrogen heat treatment is performed before the electrode wiring is formed, and a short-time heat treatment is performed after the electrode wiring is formed. That is, in this method, as shown in FIG. 2, polycrystalline silicon is deposited [FIG. 2(b)], patterned [FIG.
Formation of gate 4 and implantation of ions 5 [Fig. 2 (e)], Formation of glabella insulating film 6 and long-term high temperature hydrogen heat treatment [Fig. 2 (f)], Contact hole 8
Electrode formation is carried out through the following steps: formation of Al electrode IO [FIG. 2(g)].
[発明が解決しようとする課題]
しかし、前記の方法では電極配線形成前後に熱処理工程
が2回もあり作業性の面で問題があり、しかも長時間の
高温水素熱処理のため安全性の面で問題があった。[Problems to be Solved by the Invention] However, the above method has problems in terms of workability because it requires two heat treatment steps before and after forming the electrode wiring, and furthermore, it has problems in terms of safety due to the long-time high-temperature hydrogen heat treatment. There was a problem.
本発明は上記の点を解決しようとするもので、その目的
は、活性化Arガスにて作業性、安全性の面で良好にコ
ンタクト部のシリコン表面の酸化膜や水分を除去し、そ
の後の電極配線工程でオーミックな電極を形成すること
にある。The present invention aims to solve the above-mentioned problems, and its purpose is to remove the oxide film and moisture on the silicon surface of the contact part using activated Ar gas in a good manner in terms of workability and safety. The purpose is to form ohmic electrodes in the electrode wiring process.
[課題を解決するための手段]
本発明は、半導体装置製造工程において、コンタクトホ
ール形成後にコンタクト部を活性化Arガスにてクリー
ニングし、その後金属電極配線を形成することを特徴と
する半導体装置の製造方法に関する。[Means for Solving the Problems] The present invention provides a semiconductor device in which, in a semiconductor device manufacturing process, after forming a contact hole, a contact portion is cleaned with activated Ar gas, and then a metal electrode wiring is formed. Regarding the manufacturing method.
[作用]
コンタクトホール形成後、Arイオン注入装置にて半導
体基板表面を打つことにより、コンタクト部内に露出す
るシリコン表面の酸化膜や水分を除去することができ、
その後の金属電極配線工程でオーミックな電極を形成す
ることが可能となる。[Function] After forming the contact hole, by implanting the surface of the semiconductor substrate with an Ar ion implanter, the oxide film and moisture on the silicon surface exposed in the contact part can be removed.
It becomes possible to form ohmic electrodes in the subsequent metal electrode wiring process.
[実施例] 次に本発明を実施例を挙げて説明する。[Example] Next, the present invention will be explained by giving examples.
実施例
第1図に本発明の一実施例である薄膜トランジスタの製
造工程を示す。透明絶縁基板1上に減圧CVD法により
膜厚1000〜5000人程度の多結晶シリコン薄膜2
を堆積させた[第1図(b)]。次に前記多結晶シリコ
ン薄膜2にパターン形成した後[第1図(c) ] 、
熱酸化またはCVD法にて膜厚500〜1000人程度
のゲート絶縁膜3を積層させた[第1図(d)]。Embodiment FIG. 1 shows the manufacturing process of a thin film transistor which is an embodiment of the present invention. A polycrystalline silicon thin film 2 with a film thickness of about 1000 to 5000 layers is formed on a transparent insulating substrate 1 by low pressure CVD method.
was deposited [Fig. 1(b)]. Next, after forming a pattern on the polycrystalline silicon thin film 2 [FIG. 1(c)],
A gate insulating film 3 having a thickness of approximately 500 to 1,000 layers was laminated by thermal oxidation or CVD method [FIG. 1(d)].
その後、多結晶シリコンを膜厚2000〜4000人程
度堆積させ、バターニングしてゲート4を形成した。さ
らに必要に応じてイオン5の打ち込みによりB゛または
P゛を2〜4 x 10 ” /cm2でドープしP型
、N型領域を形成後、900℃の02で30分間処理し
活性化させた[第1図(e)〕。次に膜厚1000〜5
000人の層間絶縁膜6を形成後、多結晶シリコン中の
欠陥を水素原子で埋めるために水素プラズマ処理7を行
った[第1図(f)]。次にコンタクトホール8を設け
、コンタクト部を活性化Arガスで露出したシリコン表
面のエツチングにより酸化膜を除去し、またコンタクト
部の水分を除去した[第1図(g)]。ここで、活性化
Arガスによるクリーニング処理は、例えばインプラに
てAr”エネルギー10〜20Keyの範囲でシリコン
表面を打つことにより行われる。最後にコンタクトホー
ル8内にA1電極lOのパターン配線を行い、薄膜トラ
ンジスタを製造した[第1図(h)]。得られた薄膜ト
ランジスタのコンタクト抵抗は安定した低い値でありオ
ーミック特性を示した。Thereafter, polycrystalline silicon was deposited to a thickness of about 2,000 to 4,000 layers, and the gate 4 was formed by patterning. Furthermore, if necessary, ions 5 were implanted to dope B' or P' at 2 to 4 x 10''/cm2 to form P-type and N-type regions, and then they were activated by treatment at 02 at 900°C for 30 minutes. [Figure 1(e)]. Next, the film thickness is 1000~5.
After forming the interlayer insulating film 6 of 1,000 yen, hydrogen plasma treatment 7 was performed to fill the defects in the polycrystalline silicon with hydrogen atoms [FIG. 1(f)]. Next, a contact hole 8 was formed, and the oxide film was removed by etching the exposed silicon surface in the contact area with activated Ar gas, and moisture in the contact area was removed [FIG. 1(g)]. Here, the cleaning treatment with activated Ar gas is performed, for example, by hitting the silicon surface with Ar'' energy in the range of 10 to 20 keys using implantation.Finally, pattern wiring of the A1 electrode IO is performed in the contact hole 8. A thin film transistor was manufactured [FIG. 1(h)]. The contact resistance of the obtained thin film transistor was a stable and low value, and exhibited ohmic characteristics.
[発明の効果]
以上の説明で明らかなように本発明によれば、作業性、
安全性の面で良好にコンタクト部のシリコン表面の酸化
膜を除去することができ、コンタクト抵抗が安定した低
い値でオーミック特性を有する半導体装置を製造するこ
とが可能となる。[Effect of the invention] As is clear from the above explanation, according to the present invention, workability,
The oxide film on the silicon surface of the contact portion can be removed in a good manner from the standpoint of safety, and a semiconductor device having ohmic characteristics with a stable and low contact resistance can be manufactured.
第1図は本発明の一実施例である半導体装置の製造工程
を示す断面図、第2図は従来の半導体装置の製造工程を
示す断面図である。
1・・・透明絶縁基板、 2・・・シリコン薄膜、3・
・・ゲート絶縁膜、 4 ・・ゲート。
5・・・イオン、 6・・ 層間絶縁膜、7・・・水
素、 8 ・・コンタクトホール、9・・・Arガス、
10・・・Al電極。FIG. 1 is a sectional view showing the manufacturing process of a semiconductor device according to an embodiment of the present invention, and FIG. 2 is a sectional view showing the manufacturing process of a conventional semiconductor device. 1... Transparent insulating substrate, 2... Silicon thin film, 3...
...Gate insulating film, 4...Gate. 5...Ion, 6...Interlayer insulating film, 7...Hydrogen, 8...Contact hole, 9...Ar gas,
10...Al electrode.
Claims (1)
にコンタクト部を活性化Arガスにてクリーニングし、
その後金属電極配線を形成することを特徴とする半導体
装置の製造方法。In the semiconductor device manufacturing process, after forming the contact hole, the contact part is cleaned with activated Ar gas,
A method of manufacturing a semiconductor device, the method comprising: thereafter forming a metal electrode wiring.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3352590A JPH03236226A (en) | 1990-02-14 | 1990-02-14 | Manufacturing method of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3352590A JPH03236226A (en) | 1990-02-14 | 1990-02-14 | Manufacturing method of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03236226A true JPH03236226A (en) | 1991-10-22 |
Family
ID=12388962
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3352590A Pending JPH03236226A (en) | 1990-02-14 | 1990-02-14 | Manufacturing method of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03236226A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US12418125B2 (en) | 2020-08-31 | 2025-09-16 | Yamaichi Electronics Co., Ltd. | Impedance mismatch suppressing connector |
-
1990
- 1990-02-14 JP JP3352590A patent/JPH03236226A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US12418125B2 (en) | 2020-08-31 | 2025-09-16 | Yamaichi Electronics Co., Ltd. | Impedance mismatch suppressing connector |
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