JPH03236642A - Frame counter - Google Patents

Abstract

PURPOSE:To realize a frame counter in which number of upper limits of counters able to be in cascade connection and an optional period is set by reading a carry output and a count output of each stage with an input clock. CONSTITUTION:A carry output 171 of a 2-bit counter 161 is inputted to a FF 181, which reads the output 171 by a clock 1 and outputs a carry output 31 of an address counter circuit 21. A 2-bit counter 162 counts a signal only when the output 31 is at an L level. Succeedingly, similar operation is implemented and a 6-bit frame counter is realized. Then in order to arrange 6-bit count outputs 41-43, the outputs 41-43 of the circuits 21-23 are inputted respectively to 3, 2, 1-bit shift registers 51-53, where the signals are shifted by 3-1 bit and outputted as address outputs 61-63. An address in 6-bit comprising the outputs 61-63 is inputted to an adder 7 and addresses 81-83 summing by four are outputted. They are outputted in a same timing and the frame counter generating 6-bit address is realized.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a frame counter device used, for example, in the field of digital communications.

[Conventional technology]

For example, in the field of digital communications, a serial data stream is generated by time-division multiplexing multi-channel code groups, and data of these multi-channel code groups is sent and received via a single communication path. is being carried out. When performing time division multiplexing, it is necessary to arrange each code group at a predetermined time position, and the device that generates the basic timing used for this operation is a device called a 7-frame counter. In other words, the transmitting side sequentially arranges the data of multi-channel code groups according to the timing given by the transmitting frame counter, sends this to the receiving side via a single communication path, and the receiving side uses this data for reception. 7. Multi-channel code groups from the serial data stream according to the timing specified by the frame counter.

Data is reproduced by separating each channel one by one.

The frame counter device used for the above purpose can be realized by cascading counters.

FIG. 5 is a block diagram for explaining a conventional example of the frame counter device, and FIG.

It is a timing diagram for explaining the #IS diagram. inside,
In FIG. 6 and below, to simplify the explanation, N=
=3. The case where M=2 will be described.

Further, the numbers in FIG. 5 and FIG. 6 correspond.

5 and 6, the first 2-bit counter (
161) outputs a count output (41) in synchronization with a clock (1) input from the outside. Count output (4
When 1) becomes 3, the carry output (171) becomes 1L'. The second 2-bit counter (162) counts only when the carry output (17) is in the state of 1L'.

Similarly, the third 2-bit counter has a carry output (172
) is counted only when it is 1L'. Therefore, in FIG. 5, by cascading three 2-bit counters, the basic timing and the 6-bit address corresponding to the above-mentioned basic timing are generated.
A frame counter device is realized.

Also, 6-bit count output (41), (42)
1 (45) is input to the address decoder (91).

The address decoder (9) outputs a reset output Hf at a specific address (111 (41) in FIG. 6).

The output Q (1) of the above decoder (91 is ORed with the preset signal aD from the outside by the OR gate a2 and becomes the preset output a3. This realizes a frame counter device having an arbitrary period of j664 or less. can.

Furthermore, the 7 frame counter device can be preset at a desired timing by an external preset signal a1+.

[Problem to be solved by the invention]

Written on a general digital e-C counter.

The carry output is the output of the AND operation of the carry input and the count output. Therefore, in FIGS. 5 and 6, the carry output (171) is the second 2-bit counter (1
61) and the third 2-bit counter (162), the pulse width gradually becomes smaller from the carry output (172) to the carry output (17M). Therefore, at high frequencies where the propagation delay time of the carry output cannot be ignored, there is a problem that there is an upper limit to the number of counters that can be cascaded.

This invention was made to solve this problem, and it eliminates the upper limit on the number of counters that can be cascaded even when using a high frequency input clock, by rereading the carry output and count output using the input clock. The purpose of this invention is to realize a frame counter device having an arbitrary period.

[Means to solve the problem]

In the frame counter device according to the present invention, in order to reread the carry output and count output of the counter at each stage using the input clock, the delay time of the carry output of the counter at each stage with respect to the input clock is absorbed, and the carry This prevents the accumulation of output propagation delays.

[Effect]

In this invention, by absorbing the delay time of the carry output of each stage counter with respect to the input clock,
This makes it possible to eliminate the upper limit on the number of counters that can be connected in cascade.

〔Example〕

1 and 2 are block diagrams showing an embodiment of the present invention, and FIGS. 3 and 4 are timing diagrams for explaining FIGS. 1 and 2. FIG. inside.

The numbers in Figure 1, Figure 2 and w, Figure 3 and Figure 4' correspond.For simplicity, in Figure 3, Figure 4 and below, N:=3. The case where M=2 will be described.

1, 2, 3, and 4, the carry output (171) a, a of the first 2-bit counter (161)
1 flip-flop (1111). The first flip-flop (tSt) rereads the carry output (171) with a clock (0).

Carry output of the first address counter circuit (21) (
31) is output. Second 2-bit counter (11i2
) counts only when the carry output (31) is 1L'. The carry output (172) of the second 2-bit counter (162) is sent to the second flip-flop (18
2) and the second 7 lip-flop (182
) rereads the carry output (172) with the clock (1) and outputs the carry output (32) t- of the second address counter circuit (22). Similarly, the third 2-bit counter (165) has a carry output (32) of 1L.
’ and count the third 7 lip-flop (11B
It then outputs a carry output (173). 3rd 7 above
The lip-flop (1115) outputs the carry output (35) of the third address counter circuit (25). Therefore, by cascading the three address counter circuits described above, a 6-bit frame counter device is realized.

However, the carry output (171) of the first 2-bit counter (161), the second 2-bit counter (162)
) carry output (172) and carry output (175) of the third 2-bit counter (11i5) are as follows:
The first 7 lip flops (lal).

It is input to the second flip-flop (1112) and the third 7-lip-flop (18a), and the clock (1
), the carry outputs of the above three address counter circuits (31), (32)t (33
) are the respective count outputs (41) and (42).

(43) Yo, I'm late by the Fit clock! cormorant. Therefore, 6-bit count output (4*)t (42), (
43), the count output (41) of the first address counter circuit (21) is input to a 3-bit shift register (51). The 3-pit shift register (51) shifts the count output (41) by 3 bits in synchronization with the clock (1) and outputs an address (
61). Similarly, the count output (42) of the second address counter circuit (22) is input to the 2-bit shift register (52), and becomes the address output (62) shifted by 2 bits in synchronization with the clock (1). . Furthermore, the count output (4M) of the third address counter circuit (23) is
) is entered.

The address output (63) is shifted by one pit in synchronization with the clock (1). Furthermore, 8 which is composed of three address outputs Ca1)I Co2)t Ca5)
The bit address value is input to an adder (7). In this embodiment, the adder (7) is an adder that adds only four address values;
*yyvx value (81)# (112)t (84
5) Output. Therefore, the passage shown in FIGS. 3 and 4 is used.

Address value obtained by adding the above four values <81), (112)
j (83) are output at the same timing to realize a frame counter device that generates an lI-bit address.

Furthermore, in order to create a 7-frame counter device with an arbitrary period of 6 bits or less, we will discuss the case where the 7-frame counter device is reset with a predetermined address value (111(4) in Figures 3 and 4). think.

Address values (11) and (82) obtained by adding the above four.

(85) is input to the address decoder (91). The address decoder (9) receives the determined address value (
In this embodiment, the decode output α is 111 (41).
・Outputs. The above decode output axis is the OR gate υ
This is logically ORed with a reset signal input from the outside, resulting in a reset output of 0.

The reset output 0 is as shown in FIGS. 3 and 4, p,
3-bit serial in-parallel out shift register (
Hereinafter, it will be abbreviated as 3-bit 87P shift register. )a4
1 is input. Above 3 bits) 8/P shift register 0
is the reset signal a in synchronization with the clock (1).
The output (151) shifted by 1 bit is shifted to the first address counter circuit (21), and the output (152) shifted by 2 bits is shifted by 3 bits to the second address counter circuit (22). The outputs (153) are respectively outputted to the third address counter circuit (25).

As a result, the four address values (81)t (82)t (@!S) shown in FIGS. 3 and 4 are simultaneously reset to 10'. Therefore, the 7-frame counter device is reset at the correct timing, and a frame counter device with an arbitrary period is realized.

In this case, for example, the carry output (31) input to the second address counter circuit (2) includes the propagation delay time when passing through the first 2-bit counter (1s1) fc. The carry output includes only a delay time of 7 times and 70 tits.No matter how many stages are cascaded, the timing of the carry output input to each stage and the input clock will be the same. Therefore, there is no upper limit on the number of counters that can be cascaded, and a frame counter device with an arbitrary period can be realized.

〔Effect of the invention〕

The present invention, as described above, rereads the carry output of the counters in each stage using the input clock, and shifts the counter outputs of the counters in each stage by the required number in synchronization with the input clock.

This has the effect of eliminating the upper limit on the number of counters that can be connected in cascade and making it possible to realize a 7-frame counter device that can set any period.

[Brief explanation of drawings]

1 and 2 are block diagrams showing embodiments of the present invention,
3 and 4 are timing diagrams showing signals of each part to explain FIGS. 1 and 2, FIG. 5 is a block diagram showing an embodiment of a conventional frame counter device, and FIG. FIG. 5 is a timing diagram showing signals of various parts for explaining FIG. 5; In the figure, (0 is the clock, (31) to (2N)
is the first to first address counter circuit, (51)
~(SN) are N shift registers from N bits to 1 pit, (7) is an (N+1) adder, (9) is an address decoder, a3 is a 2-input OR game), and a41 is N
Bit serial in parallel out shift register/,
(flit) ~ (11iN) is the first to first Mk”
The counters (1·1) to (lilN) are first to first flip-flops. The same reference numerals in the figures indicate the same or equivalent parts.

Claims (1)

[Scope of Claims] An address counter circuit whose constituent elements include an M-bit counter that receives an externally input clock and a flip-flop that receives the carry output of the counter and uses the clock as a trigger signal, N stage frame counter circuits are sequentially cascaded from the counter circuit to the first address counter circuit, and the outputs of the first address counter circuit to the Nth address counter are respectively input, and the corresponding address counter circuits are cascaded. N bits, (N-
1) Input N shift registers from the N-bit shift register to the 1-bit shift register and the outputs of the N shift registers to be shifted in synchronization with the above clock by the number of shifts decreased by 1 bit. An adder that adds (N+1) and outputs the result, an address decoder that receives the output of the adder as input, and two inputs that perform a logical OR operation between the output of the address decoder and a reset signal input from the outside. The OR gate and the output of the two-input OR gate are input, and a reset signal is output to the N address counter circuits from the first address counter circuit to the N-th address counter circuit in synchronization with the clock. 1. A frame counter device comprising: an N-bit serial-in-parallel-out shift register. (However, M and N are any positive integers.)