JPH0323667A - Gate array - Google Patents

Abstract

PURPOSE:To enable an analog circuit to be wired easily by the master slice system and to enable the circuit properties to be maintained fully by opposing large and small basic cells of transistor size at an opposing row for the row of basic cell. CONSTITUTION:Basic cells A and B are placed alternately and a basic cell 4a with a large transistor width and a basic cell 4c with a small transistor width is placed at both sides of a basic cell 4b of normal size. The cells 4c and 4b are placed at positions opposing the cell 4a and opposing the cell b, respectively. Also, an I/O cell 2 is formed at the periphery of a semiconductor substrate 1 and an I/O pad 3 for taking out is formed on the cell 2. It is possible to wire a multilayer aluminum wiring using this gate array by the master since system, thus forming a D/A converter.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a semiconductor device, and particularly to a CMOS gate array structure for forming an analog circuit by applying a mask slicing method.

(Prior Art) In a conventional gate array, as shown in FIG. In addition to defining input/output (I/O) pads 3, basic cells 4 consisting of transistors, resistors, etc. are regularly arranged as element areas with wiring areas C in between, and these element areas are divided as necessary. Semiconductor integrated circuit devices using the mask slicing method have become widely used, in which a desired circuit is formed by creating a wiring mask to connect transistors and resistors using wiring patterns. There is.

In such a mask slicing type semiconductor integrated circuit device, a plurality of columns of basic cells 4 are formed in the vertical direction, and wiring channels are formed between the basic cell columns.

As shown in an example of an enlarged plan view in FIG. 9, each basic cell has p-type transistors Pi, P2 having a common source or drain in the n-silicon substrate 1, and In the p-type well region 8, n-type transistors N1 and N2 having a common source or drain are provided. That is, an n-type source/drain region 7N is formed in a p-type well region 8 formed in an n-silicon substrate 1, and a p-type well region 8 is formed in the n-silicon substrate 1.
A p-type source/drain region 7P is formed outside the type well region 8. Further, a polysilicon gate electrode 5.6 is formed so as to sandwich each of these source*drain regions 7N and 7P, and the polysilicon gate electrode 5.6 is sandwiched between the source*drain regions 7N and 7P, and the polysilicon gate electrode 5.6.
The structure is such that various functional cells can be realized by wiring connections between the cells. An equivalent circuit of this basic cell is shown in FIG.

Digital circuits such as inverters, NAND circuits, NOR circuits, flip-flop circuits, etc. are constructed by wiring the array of basic cells using a mask slicing method, and each gate is further wired to form a logic circuit. In this way, the basic cell is prefabricated and only the wiring process is required, which has the advantage of shortening the development time.

However, in applications other than digital systems such as computers, it is often convenient to be able to integrate a small amount of analog circuits. Especially regarding LSI used in automobiles,
Since analog signals are involved in processing inputs from sensors and outputs to actuators, integrating analog circuits into gate arrays has the advantage of shortening the development time until implementation and speeding up the development of the entire system. be.

Therefore, as shown in FIG. 11, it may be possible to incorporate analog cells 10, which constitute analog circuits such as operational amplifiers, comparators, and D/A converters, into the gate array in advance. In this case, although it is expected that the analog circuit will have good characteristics, in this method, the number of analog cells 10 and the circuit type are limited in advance, which limits the range of application, and as a result, parts may be required at the mounting stage. There was a problem in that the development time for the system could not be reduced much.

For this reason, in system development, it has become necessary to adopt the mask slicing method including such analog circuits.

However, conventional gate arrays for digital circuits are all arrays of the same basic cells 4, making it difficult to form analog circuits that require various transistor sizes. Since it is possible to connect as many transistors as the transistor size ratio, the wiring inside the analog cell becomes long, and the characteristics of the analog circuit are not sufficient due to parasitic resistance and capacitance. The problem was that I couldn't do it.

Also, when configuring memory using the mask slice method,
A device in which a transmission gate transistor is included in the basic cell was proposed (Japanese Patent Laid-Open No. 58-139
446), and not only such digital circuits, but also
This method is also applicable to analog cells.

However, in this case, the number of basic cells becomes enormous, and when there are many digital circuits, there is a problem in that the efficiency of transistor utilization decreases significantly.

(Problems to be Solved by the Invention) As described above, in conventional gate array ICs, when attempting to incorporate an analog circuit using the mask slicing method, the wiring length becomes long, resulting in an analog circuit with poor characteristics such as oscillation. In addition, there were disadvantages such as the number of basic cells becoming enormous.

The present invention has been made in view of the above-mentioned circumstances, and it is an object of the present invention to enable analog circuits to be easily incorporated into a mask-sliced gate array with good characteristics.

[Structure of the invention]

(Means for Solving the Problems) Accordingly, in the present invention, a column of any pair of opposing basic cells is configured to include regions in which the transistor sizes of the opposing basic cells are different.

(Function) According to the above configuration, it is possible to form regions in which the transistor sizes of opposing basic cells are different, so that wiring routing can be reduced, and even in the mask slicing method, parasitic capacitance can be suppressed and reliability can be improved. This makes it possible to integrate high-performance analog circuits.

(Example) Hereinafter, examples of the present invention will be described in detail with reference to the drawings.

In FIG. 1, first and second basic cell columns A and B are arranged alternately as shown in the gate cell array according to the embodiment of the present invention, and each column has 112 diagrams (a) to (6).
), as shown in an enlarged view of each basic cell, there are large basic cells 4a (W=1.
3) and a small basic cell 4c with a small transistor width W (W
= 0.7), and in the first and second basic cell rows A and B, small basic cells 4 c s are arranged at positions opposite to the large basic cells 4 a, and small basic cells 4 c s opposite to the normal basic cells 4 b. ? Ordinary basic cells 4b are arranged at the base.

Here, the structure of each basic cell is exactly the same as the structure of the conventional example shown in FIG. In addition, an input/output (I/O) cell 2 is formed on the periphery of the semiconductor substrate 1,
On this input/output cell 2, input/output for retrieval (
I/O) pad 3 is formed.

Using this gate array, a D/A converter such as the equivalent circuit shown in FIG. 3 can be constructed by wiring multilayer aluminum wiring by a mask slicing method.

This D/A converter is composed of a resistance chain (resistance ladder) 11a formed by connecting resistances 11 in series, and a CMOS transmissing gate 12 whose input is the connection point of these resistances. And the resistance chain 11a is the power supply 13
CMOS}transmission gate 12 which is connected to each position by resistor-dividing between and ground 14
is selected and output as an analog quantity to outputs 15 - 15n. (actually D/A
When performing conversion, it is necessary to adjust the arrangement of the CMOS translation gate 12, but this is omitted here for the sake of brevity. ) Then, as a connection example is shown in FIG. 4, the large basic cell 4a
is used as the resistor 12, and the small basic cell 4c opposed thereto is used as the CMOS transmission gate 12, and a D/A converter is formed by arranging the pair of two large and small basic cells facing each other. In the figure, 13 is a power supply, and 14 is a ground.

Here, since each resistor 11 is constituted by a large basic cell 4a of the circuit shown in FIGS. 1 and 2,
While having a high resistance, the CMOS transmitting gate 12 is composed of a small basic cell 4c facing thereto. Therefore, in order to reduce current consumption, each resistor 11
It is necessary to increase the large basic cell 4a with a resistor of 12
By connecting the small basic cell 4c facing the CMOS transmission gate 12 with wiring so as to use it as a CMOS transmission gate 12, the height resistance can be easily obtained, and the wiring can be routed over the shortest distance.

Therefore, it is possible to easily form a small-sized analog/digital circuit with good characteristics without the occurrence of parasitic resistance or the like using the mask slicing method.

Embodiment 2 Next, a case of configuring an operational amplifier as a second embodiment of the present invention will be described. The equivalent circuit of this operational amplifier is shown in Figure ji5.

This operational amplifier includes first to fifth p-channel transistors TPI to TP5, first to m3 leakage channel transistors TNI to TN3, and capacitors. It is composed of song c. Here, the terminal 2o is for current setting, and is grounded via an external resistor.

The input terminals 21.22 are then connected to the gate terminals of the fourth and fifth p-channel transistors TP4 and T P 5'. Here, as indicated by 0 in the figure, the first to fifth p-channel transistors TPI to TP5 have a ratio of 1.3:3.9.
:2.3:1:1. Further, the first to third n-channel transistors TNI to TN3 have a size ratio of 0.7:0.7:1.7, respectively.

Here, the gate cell array is formed in the same manner as in the first embodiment shown in FIG. 1, and wiring is performed as shown in FIG. 6.

Whereas forming a circuit with such a cell ratio using a conventional gate array would require at most 45 basic cells, this method only requires the use of 8 basic cells, significantly reducing the cost. It becomes possible to reduce the chip size.

Furthermore, since the wiring length can be short, the parasitic resistance and parasitic capacitance associated with the wiring are small, and the characteristics of the operational amplifier are extremely good.

As described above, according to the present invention, it is possible to wire a digital analog circuit using the mask slice method while ensuring the characteristics of the analog circuit. The method of the present invention is particularly effective in analog circuits such as operational amplifiers whose frequency characteristics are degraded by parasitic elements.

Note that there are two possible methods for configuring a logic circuit using such basic cells as shown below.

One is to wire small basic cells in parallel in consideration of driving force. For example, two small basic cells 4C are connected in parallel to form an inverter.

The other method is to use each cell as is, check its operating speed through simulation, and verify the operation of the entire circuit.

In this way, it is possible to perform appropriate wiring while taking advantage of the degree of freedom in consideration of the characteristics of the basic cell circuit of the present invention.

In addition to the cell arrangement shown in FIG. 1, the gist of the present invention is to increase the types of cell sizes of the basic cells and form them so that the cell sizes sequentially increase or decrease, as shown in FIG. 7. It can be changed as appropriate without departing from the above. In the case of the example shown in FIG. 7, it is difficult to shape the digital circuit, but if there are many analog circuits, wiring can be efficiently done using the mask slicing method.

〔Effect of the invention〕

As explained above, according to the semiconductor device of the present invention, in the gate array IC, for the column of basic cells,
Basic cells with large and small transistor sizes are placed in opposing columns, making it easy to create analog circuits using the mask slicing method. It becomes possible to wire the circuit and maintain good characteristics of the analog circuit.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the basic cell structure of a gate array according to an embodiment of the present invention, FIGS. 2(a) to 2(e) are diagrams of each cell of the basic cell, and FIG. 3 is a D/A diagram. Figure 4 shows the equivalent circuit of the converter, Figure 4 shows the connection wiring, Figure 15 shows the equivalent circuit of the operational amplifier, Figure 6 shows the connection wiring, and Figure 7 shows the modification of the gate array. 8 shows a conventional gate array, FIG. 9 shows an enlarged view of a unit cell, and FIG. 10 shows a modification of the basic cell of the present invention.
11 are diagrams showing the circuit configuration of a conventional gate array. 1... Board, 2... Input/output cell, 3... Input/output (
I/O) pad, 4...basic cell, 5.6...
Gate electrode, 6P, 6N... Gate electrode, 7P, 7N
. . . Source ◆ Drain region, 8 . . . P-type well region, 11. ...Resistance, 11a...Resistance chain (resistance ladder), 12...CMOS transmission gate,
13.゛...Power supply, 14...Ground, 15■...
15n...output.

Claims (1)

[Claims] (1) In a gate array in which gates each having at least one pair of p-channel MOS transistor and n-channel MOS transistor having a common gate electrode are arranged in a plurality of columns across a wiring region, the gates are arranged in opposing positions in adjacent columns. A gate array characterized in that transistors formed include regions formed to have mutually different widths.