JPH03237691A - Semiconductor memory - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor memory device composed of bipolar transistors.

RAMs used in buffer memories and the like require high speed performance, so they are composed of bipolar transistors. In such a RAM, read and write operations are performed by flowing a read current and a write current through the word line and bit line of a selected cell in order to improve the read and write speed. In such a RAM, in order to particularly improve the write speed, it is necessary to increase the write current flowing through the bit line on the side where the H level is written.

[Prior Art] In order to improve the write speed of a RAM configured with bipolar transistors, it is desirable to increase the write current flowing from the word line to the H-level bit line via the relevant cell. In other words, increasing the write current of the H level write side bit line can quickly remove the charge accumulated on the L level side of the cell and shorten the time required to turn off the L level write side. be.

A conventional example of this will be explained with reference to FIGS. 6 and 7. The RAM is usually composed of a cell area l for storing cell information and a control unit 2 for controlling writing and reading of cell information to and from the cell area l. has been done. In the cell region l, a large number of word lines WL 1 -WL n are connected to an address decoder 3, and when an address is selected, the word lines WL 1 - WL n are connected by the action of the address decoder 3.
For example, one of the word lines WL becomes H level.
When I becomes H level, the cell information of the cells Sll to Sin connected to the word line WLI can be read or written to each cell using a pair of bit lines BLI, BL2 to BLn-1°BLn. Note that each cell is composed of a flip-flop circuit using bipolar transistors.

Each column C1 to Cn, which is composed of a pair of bit lines and a large number of cells, has the same configuration, so below column C1
I will only explain about.

The bit lines BLI, BL2 are provided with multi-emitter transistors T rl, T r2 . for bit line selection. T r3
゜Tr4 is connected, and these transistors Trl,
Tr2. T r3. Tr4 operates synchronously based on a bit line selection signal output from the column decoder to each input terminal BS. A pair of transistors Tr5. whose emitters are connected to the bit lines BLI, BL2. Tr
The base of 6 is connected to a read/write amplifier 4 in the control section 2, and operates based on a control signal output from the read/write amplifier 4 during read and write operations. Further, a pair of transistors Tr7 and Tr8 whose bases are connected to the bit lines BLI and BL2 are transistors Tr7 and Tr8 whose emitters are operated based on the bit line selection signal.
When the transistor Tr9 is turned on, the potential difference between the bit lines BL1 and BL2 is detected and transmitted after the sense amplifier 5 in the control section 2.

The read/write amplifier 4 includes a transistor Trio for controlling the write current flowing to the bit lines BLI and BL2.
, the base of Trll is connected.

The emitter of the transistor Trlo is connected to the emitter of the transistor Tr3 for flowing the write current IW to the bit line BL2, and the emitter of the transistor Trll is connected to the emitter of the transistor Tri for flowing the write current IW to the bit line BLI. . Then, when the transistors TrlO and Trll are turned on, the transistors T rl and T r3 are turned off.

Next, a case will be described in which cell information is read from cell Sll, for example, in the cell area ■ configured as described above.
When the L level chip select signal SGl shown in FIG. 7 is input to the input terminal C8 of the control unit 2 and the address selection signal for selecting the cell Sll is output, the word line WLI is set to the H level by the operation of the address decoder 3. At the same time, an H level signal is output from the column decoder to the input terminal BS, and column C1 is selected, so that cell S1
1 is selected.

On the other hand, as shown in FIG. 7, when the write control signal SG2 at the H level is output to the input terminal WE of the control unit 2 in synchronization with the chip select signal SGI at the L level, the read/write amplifier 4 outputs the transistors Trio, An H level base voltage is supplied to Trll, and the transistor Trll
O, Trll is turned on.

Then, transistors TrlO and Trll are turned on, and transistors T rl and T r3 are turned off.

At the same time, the read/write amplifier 4 connects the bit line BLI.
, BL2 are connected to the bases of the transistors Tr5゜Tr6 with a lead level (the H level of the cell).

Supply voltage (intermediate between L level).

Therefore, for example, when the cell S11 is selected and its cell information is read, the transistors Tr2 and Tr4 are turned on. For example, if the cell on the bit line BLl side in the cell 811 is written in the on state, the word line Transistor Tr2 from WLI via cell Sll and bit line BLI
With the read current IR flowing in the bit line BLI
becomes H level, and the potential of the bit line BLI is read out by the sense amplifier 5 via the transistor Tr7.

In addition, a read current IR flows into the bit line BL2 from the transistor Tr6 turned on by the operation of the read/write amplifier 4 to the transistor Tr4, and the bit line BL2 becomes L level with the read current, and the bit lines BLI, BL2 The potential difference is detected and transmitted after the sense amplifier 5.

Next, the case of writing cell information to the cell Sll will be described.

As shown in FIG. 7, during writing, the write control signal SG
2 becomes L level, and when the write control signal SG2 is inputted to the input terminal WE of the control section 2, the read/write amplifier 4 outputs the signal when the data signal inputted to the input terminal DA of the control section 2 is at the H level. is the transistor T r6. T
rlo is turned on and transistor T r5.
T rll is turned off, and in the case of L level, this is reversed.

That is, when writing H-level information to the bit line BLI side of the cell 811, an H-level signal is input to the input terminal DA, and based on this, the read/write amplifier 4 outputs the transistors Tr6. An H level signal is applied to the base of transistor Tr5. T
An L level signal is output to the base of rll. Then, the transistors T rl, T r2° T r4 .
Tr6 is turned on, and the transistor Tri is connected to the H level side bit line BLl from the word line WLI through the cell Sll.
A write current IR+IW flows through Tr2, and a write current IR flows from the transistor Tr6 to the transistor Tr4 on the L level side bit line BL2.

Therefore, with the above configuration, during writing, the write current IR+IW, which is larger than the read current, is applied to the cell Sll.
The write current IR+IW flows from the write current IR+IW to the H-level bit line BLI, and this write current IR+IW contributes to shortening the time required to turn off the L-level transistor of the cell Sll.

[Problems to be Solved by the Invention] In the RAM having the above configuration, the larger the write current IR+IW flowing through the H level side bit line and the larger the current ratio with the write current IR flowing through the L level side bit line. This improves the writing speed, but each word line has many bits connected to it, and when a writing operation is performed on those many bits at the same time, the writing current on the H level side of the cell selected by each bit increases. As the write current increases, a voltage drop occurs in the address decoder 3 due to the write current, making it impossible to supply a sufficiently high H level voltage to the writing side bit line of each bit, or a large voltage that flows from the word line to each bit at the same time. The word line may be disconnected due to the write current. As a result, since there is a limit to the increase in the write current, there is also a limit to the improvement in the write speed by increasing the write current. Furthermore, if an attempt is made to increase the write current ratio by reducing the write current IR on the L level side, that is, the read current IR, a problem arises in that the read speed decreases.

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor memory device that improves the writing speed of cell information while preventing address decoders and word lines from becoming a load on the writing current, and does not reduce the reading speed.

[Means for Solving the Problems] FIG. 1 is a diagram illustrating the principle of this invention. That is, in the semiconductor memory device, a specific cell S is selected by selecting a word line WL and a pair of bit lines BL, the same read current is applied to each bit line BL during a read operation, and the same read current is applied to each of the bit lines BL during a write operation. An H-level write current larger than the read current is passed through one bit line BL of the pair of bit lines, and an L-level write current having the same value as the read current is passed through the other bit line BL. and,
Control for temporarily adding a write additional current to the bit line BL through which the H level measurement write current flows in addition to the H level measurement write current for a time width shorter than the time width for flowing the H level measurement write current. The circuit 11 connects the pair of bit lines B
Connected to L.

[Operation] When a write operation is performed on the selected cell S, H
In addition to the normal write current, an additional write current is temporarily passed through the level side bit line BL, so the write current ratio can be increased without reducing the read current, and the additional write current is instantaneously passed. Therefore, the address decoder or word line does not become a load for the write current.

[Example] An example embodying the present invention will be described below with reference to FIGS. 2 to 5. Note that the same constituent parts as in the conventional example are given the same reference numerals, and the explanation thereof will be omitted, and only the same constituent parts as in the conventional example will be explained.

As shown in FIG. 2, multi-emitter transistors Tr21, Tr22, and Tr23 are connected to the bit line BLI to flow a write current or a read current.
is connected to the bit line BL2, and a transistor T is also connected to the bit line BL2.
r24, Tr25, and Tr26 are connected. When each transistor is turned on, a read current IR flows through the transistors Tr23 and Tr26.
A write current IW flows through the transistors Tr22 and Tr25, and an additional write current IWI flows through the transistors Tr21 and Tr24. Here is the current IR.

IW is set to the same value as in the conventional example. The emitter of the transistor Tri1 is connected to the emitter of the transistor Tr22, and the emitter of the transistor TrlO is connected to the emitter of the transistor Tr25. When the transistors TrlO and Trll are turned on, the transistors Tr22 and Tr25 are turned off. It has become so.

The emitters of transistors Tr27 and Tr28 are connected to the emitters of transistors Tr21 and Tr24, so that when transistors Tr27 and Tr28 are turned on, transistors Tr21 and Tr24 are turned off. Transistor Tr27,
The base of Tr28 is connected to a pulse supply circuit 6 provided in the control section 2, and transistors Tr27 and Tr28 operate based on the output signal from the pulse supply circuit 6.

The pulse supply circuit 6 will be explained according to FIGS. 3 and 4. The input terminal of the OR circuit 7a of the pulse supply circuit 6 is connected to the input terminal C8 and the input terminal WE, and the OR circuit 7a is connected to the input terminal C8 and the input terminal WE.
The input terminal of b is connected to the input terminal DA. O
The output terminal of the R circuit 7a is connected to a PG (pulse generator) circuit 8, and the output signal of the PG circuit 8 is sent to the OR circuit 7.
c and 7d, respectively. The output signal of the OR circuit 7b is output to the OR circuit 7d, and the output signal of the OR circuit 7b
The NOR output signal obtained by inverting the output signal of is sent to the OR circuit 7C.
It is output to . The output signal of the OR circuit 7c is output to the base of the transistor Tr27, and the output signal of the OR circuit 7c is outputted to the base of the transistor Tr27.
The output signal of the circuit 7d is output to the base of the transistor Tr28.

To explain the PG circuit 8 according to FIG. 4, the input terminal Ti
Three stages of NO'R circuits 9a, 9b, and 9c are connected in series, and the output signal of the NOR circuit 9C is the same as that of the even stage NOR circuit.
The signal is output to the NAND circuit 10a via the circuits 9d to 9n, and is also directly output to the NAND circuit 10b. Then, the output signals of each NAND circuit 10a, 10b are input to other NAND circuits, and the NAND circuit l
The output signal of Ob is output from the output terminal To.

Therefore, in such a PG circuit 8, when an H level human input signal is input to the input terminal Ti, an H level signal is input to the output terminal To.
When a high level signal is output and the input signal shifts from the H level to the L level, the output signal output from the output terminal To is delayed by the operating time of the NOR circuits 9a to 9c.
level to L level, and further NOR circuit 9d~
It returns to H level with a delay of 9n operation time. Also, the input signal input to the input terminal Ti changes from L level to H level.
When shifting to the H level, the output signal output from the output terminal TO is fixed at the H level.

Next, the operation of the RAM configured as described above will be explained.

First, a case will be described in which a cell Sll is selected and the cell information of the cell Sll is read.

In this case, the address decoder 3 selects the word line WLI.
becomes H level, and a human input signal of H level is input to the input terminal BS by the column decoder. Further, as in the conventional example, the L level chip select signal S61 is input to the input terminal C8 of the control section 2, and the H level write control signal SG2 is input to the input terminal WE. Then, regardless of whether the data signal input to the input terminal DA of the control unit 2 is at H level or L level, an H level signal is output from OR circuits 7c and 7d of pulse supply circuit 6, and based on the output signal, Transistor Tr27,
Both Tr28 are turned on, and an H level base voltage is supplied from the read/write amplifier 4 to the transistors TrlO and Trll, thereby turning on the transistors TrlO and Trll.

Further, the control unit 2 controls the transistor T r5. T r
A base voltage (read level) at an intermediate level between H level and L level is inputted to the base of 6.

Therefore, in the above state, transistors Tr23 and Tr26 are turned on in column CI, and if, for example, cell Sll stores H-level cell information on the bit line BL2 side, the bits are turned on as shown in FIG. The line BLI includes transistors Tr5 to Tr5.
A read current IR flows through bit line BL2 from word line WLI to cell Sll and transistor T.
A read current IR flows through r26. As a result, a read current IR similar to that of the conventional example is caused to flow through the bit lines BLI and BL2, and based on this read current IR, cell information is transferred to the transistors Tr7.
The signal is read out to the sense amplifier 5 via Tr8.

Next, a case will be described in which a write operation is performed to invert the cell information of the cell Sll from this state.

Now, with the transition to the write operation, the write control signal SG2 at the L level is input to the input terminal WE, and the H level is input to the input terminal DA of the control unit 2 in order to write the H level to the bit line BLI side of the cell Sll. When the signal TrlO is input from the read/write amplifier 4,
An H level signal is input to the base of the transistor Trll, and an L level signal is input to the base of the transistor Trll.
IO is turned on and transistor Trll is turned off.

Then, the transistors Tr22, Tr23, T
r26 is turned on and bit line BLI is turned on as shown in FIG.
The current flowing in bit line BL2 is increased to IR+IW, and the current flowing in bit line BL2 is increased to IR+IW.
The current flowing through is maintained at IR.

From this state, the NOR circuits 9a, 9b, 9c of the PG circuit 8
After a delay time tl approximately corresponding to the signal transmission time, an L level signal is output from the OR circuit 7c of the pulse supply circuit 6 to the base of the transistor Tr27, turning off the transistor Tr27 and turning on the transistor Tr21. Then, as shown in FIG. 5, the current flowing through the bit line BLI is added with the write additional current and becomes IR+IW+.
IWl is increased, and this state is increased to N of even stages of the PG circuit 8.
It continues for a delay time t2, which is approximately equivalent to the signal transmission time of the OR circuits 9d to 9n, and then the transistor T
r27 is turned on, transistor Tr21 is turned off, and the current flowing through the bit line BLI returns to IR+'IW. Note that if the minimum time for flowing the write current IR+IW is, for example, 10 ns according to the TWW standard, the PG is set so that the time t2 for adding the write additional current is about 8 ns.
The number of stages of NOR circuits 9d to 9n of circuit 8 is adjusted. In addition, when writing H level cell information to the bit line BL2 side, an L level signal is input to the input terminal DA, causing the operation of transistors TrlO and Trll and the transistor T.
The operations of r27 and Tr28 are reversed and the bit line BL2
A large write current will flow to the side.

As described above, in this RAM, when performing a write operation to each cell, the bit line on the side where H level cell information is written is supplied with a PG current in addition to the normal write current IR+IW.
Based on the pulse signal generated by the circuit 8, a larger write current IR+IW+IW1 is temporarily caused to flow. As a result, especially when performing a write operation that inverts cell information, the accumulated charge of the transistor that is on in the cell is quickly removed, and the transistor on the L level side that was previously on is immediately removed. Turn it off immediately,
Since the transistor on the H level side can be quickly turned on, the writing speed can be improved.

Since the large write current IR+IW+IW1 is temporarily passed for a shorter time than the time for which the normal write current IR+IW is made to flow, the address decoder 3 and word line WLI do not become a load on the write current IR+IW+IW1.

[Effects of the Invention] As detailed above, the present invention improves the writing speed of cell information while preventing the word line or address decoder from becoming a load on the writing current, and does not reduce the reading speed. It exhibits excellent effects that can provide a semiconductor memory device.

[Brief explanation of drawings]

FIG. 1 is a diagram illustrating the principle of this invention, FIG. 2 is a circuit diagram showing an embodiment of a semiconductor memory device embodying this invention, FIG. 3 is a circuit diagram showing its pulse supply circuit, and FIG. A circuit diagram showing the PG circuit in the pulse supply circuit, FIG. 5 is a waveform diagram showing the operation of one embodiment, FIG. 6 is a circuit diagram showing a conventional example related to this invention, and FIG. 7 shows the operation of the conventional example. FIG. FIG. 1 is a diagram explaining the principle of the present invention. In the diagram, WL is a word line, BL is a bit line, S is a cell, and 11 is a control circuit. Figure 3 is a circuit diagram showing the pulse lI circuit. Figure 4 is a circuit diagram showing the PG circuit. Dark form map showing the ih work of

Claims (1)

[Claims] 1. A specific cell (S) is selected by selecting a word line (WL) and a pair of bit lines (BL), and each bit line (BL) has the same A read current is applied, and during a write operation, one bit line (BL) of the pair of bit lines receives an H higher than the read current.
A semiconductor memory device in which a level side write current is passed through the other bit line (BL), and an L level side write current having the same value as the read current is passed through the other bit line (BL), the bit line (BL) through which the H level side write current is passed. A control circuit (11) for temporarily applying a write additional current in addition to the H level side write current for a time width shorter than the time width for flowing the H level side write current is provided to the pair of bit lines (BL). A semiconductor memory device characterized by being connected.