JPH0323928U - - Google Patents
Info
- Publication number
- JPH0323928U JPH0323928U JP1989085569U JP8556989U JPH0323928U JP H0323928 U JPH0323928 U JP H0323928U JP 1989085569 U JP1989085569 U JP 1989085569U JP 8556989 U JP8556989 U JP 8556989U JP H0323928 U JPH0323928 U JP H0323928U
- Authority
- JP
- Japan
- Prior art keywords
- protruding electrode
- electrode portion
- protruding
- integrated circuit
- view
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W44/00—Electrical arrangements for controlling or matching impedance
- H10W44/20—Electrical arrangements for controlling or matching impedance at high-frequency [HF] or radio frequency [RF]
- H10W44/203—Electrical connections
- H10W44/209—Vertical interconnections, e.g. vias
- H10W44/212—Coaxial feed-throughs in substrates
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
- H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Description
第１図は本考案の一実施例の断面図、第２図は
第１図の切断面線−から見た断面図、第３図
は基板１４の上部からみた平面図、第４図は他の
実施例の突起電極２２付近の断面図、第５図は本
考案の他の実施例の突起電極２５付近の断面図、
第６図は第５図に示される実施例の第５図の下方
からみた底面図、第７図は本考案のさらに他の実
施例の突起電極２８の断面図、第８図は第７図に
示される実施例の突起電極２８を示す底面図、第
９図は本考案の他の実施例の基板３１を示す断面
図、第１０図は第９図に示される基板３１の平面
図、第１１図は本考案の他の実施例の基板３７の
平面図である。 １……半導体集積回路素子、２……サブストレ
ート、３，５，８……導体、６，９……パツド、
７，２３，２６，２９……第１突起電極、１０，
２４，２７，３０……第２突起電極、１３，２２
，２５，２８……突起電極。
第１図の切断面線−から見た断面図、第３図
は基板１４の上部からみた平面図、第４図は他の
実施例の突起電極２２付近の断面図、第５図は本
考案の他の実施例の突起電極２５付近の断面図、
第６図は第５図に示される実施例の第５図の下方
からみた底面図、第７図は本考案のさらに他の実
施例の突起電極２８の断面図、第８図は第７図に
示される実施例の突起電極２８を示す底面図、第
９図は本考案の他の実施例の基板３１を示す断面
図、第１０図は第９図に示される基板３１の平面
図、第１１図は本考案の他の実施例の基板３７の
平面図である。 １……半導体集積回路素子、２……サブストレ
ート、３，５，８……導体、６，９……パツド、
７，２３，２６，２９……第１突起電極、１０，
２４，２７，３０……第２突起電極、１３，２２
，２５，２８……突起電極。
Claims (1)
- 【実用新案登録請求の範囲】 集積回路の突起電極が、 電気信号が入力または出力される第１突起電極
部分と、 第１突起電極部分を少なくとも部分的に囲んで
配置され、かつ共通電位とされる第２突起電極部
分とによつて構成されることを特徴とする集積回
路の突起電極の構造。
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1989085569U JPH0323928U (ja) | 1989-07-19 | 1989-07-19 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1989085569U JPH0323928U (ja) | 1989-07-19 | 1989-07-19 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0323928U true JPH0323928U (ja) | 1991-03-12 |
Family
ID=31634780
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1989085569U Pending JPH0323928U (ja) | 1989-07-19 | 1989-07-19 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0323928U (ja) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006156820A (ja) * | 2004-11-30 | 2006-06-15 | Toshiba Corp | 回路基板 |
| US8384213B2 (en) | 1996-12-04 | 2013-02-26 | Seiko Epson Corporation | Semiconductor device, circuit board, and electronic instrument |
| JP2014093339A (ja) * | 2012-11-01 | 2014-05-19 | Nippon Telegr & Teleph Corp <Ntt> | 実装方法 |
-
1989
- 1989-07-19 JP JP1989085569U patent/JPH0323928U/ja active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8384213B2 (en) | 1996-12-04 | 2013-02-26 | Seiko Epson Corporation | Semiconductor device, circuit board, and electronic instrument |
| JP2006156820A (ja) * | 2004-11-30 | 2006-06-15 | Toshiba Corp | 回路基板 |
| JP2014093339A (ja) * | 2012-11-01 | 2014-05-19 | Nippon Telegr & Teleph Corp <Ntt> | 実装方法 |