JPH0324069B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an improvement in a method for manufacturing a complementary MOS semiconductor device.

As is well known, complementary MOS semiconductor devices (hereinafter referred to as
CMOS) is a p-channel transistor on the same substrate.
This forms an n-channel Tr. especially,
With the recent trend toward higher density and higher integration of CMOS, there is a demand for the establishment of miniaturization technology.

By the way, conventional CMOS is manufactured by the method shown below.

First, for example, an n-type (100) silicon substrate 1
A resist pattern 3 on which a thermal oxide film 2 is grown, and the planned well area is removed by photolithography.
After forming this, using this as a mask, boron is ion-implanted under conditions of, for example, 100 keV and a dose of 8.5×10 ¹² cm ^-2 to form a boron ion-implanted layer 4 on the substrate 1 (as shown in FIG. 1A). Subsequently, the resist pattern 3 is removed, and the ion implantation layer 4 is
C. for 30 hours to form a p-well region 5, and after removing the thermal oxide film 2 by etching, a thermal oxide film 6 and a silicon nitride film 7 are again formed one after another (as shown in FIG. 1B). Subsequently, the field portions of the silicon nitride film are selectively etched using photoetching technology to form silicon nitride film patterns 7a to 7.
c (as shown in Fig. 1c).

Next, a resist pattern 8 covering areas other than the p-well region 5 is formed by photolithography, and using the resist pattern 8 and silicon nitride film pattern 7b as masks, for example boron is applied at an acceleration voltage of 40 keV and a dose of 8×10 ¹³ cm ^-2 After ion implantation under the conditions of
A p ⁺ layer 9 for preventing field inversion is formed by thermal diffusion (as shown in FIG. 1d). Subsequently, the resist pattern 8 is removed, and a resist pattern 10 covering the p-well region 5 is formed again by photolithography. Using the resist pattern 10 and the silicon nitride film patterns 7a and 7c as masks, for example, phosphorus is applied at an acceleration voltage of 10keV. After ion implantation at a dose of 5×10 ¹² cm ^-2 , thermal diffusion is performed to form an n ⁺ layer 11 for preventing field inversion (first
(illustrated in Figure e). Continuing, resist pattern 10
was removed, and selective oxidation was performed in a high temperature wet atmosphere using the silicon nitride film patterns 7a to 7c as oxidation-resistant masks to form a field oxide film 12 (as shown in FIG. 1f).

Next, a thermal oxide film is grown on the island-shaped n-type silicon substrate 1 region and the p-well region 5 separated by the field oxide film 12, a polycrystalline silicon film is further deposited, and phosphorus is diffused into this polycrystalline silicon layer. Do this. Next, the polycrystalline silicon layer is patterned to form gate electrodes 13 ₁ , 13 ₂ , and the thermal oxide film is etched using this as a mask to form gate oxide films 14 ₁ , 14 ₂ . Boron is ion-implanted into one region and arsenic is ion-implanted into the island-shaped p-well region 5 to form p ⁺ type source and drain regions 15 ₁ , 16 ₁ and n ⁺ type source and drain regions 15 ₂ and 16 _{2 .} (as shown in Figure 1g). After that, a CVD-SiO ₂ film 17 is deposited on the entire surface according to a conventional method, contact holes 18 ₁ to 18 ₄ are opened in this, and then an Al film is deposited and patterned.
CMOS is manufactured by forming Al wirings 19 to 22 (as shown in FIG. 1h).

However, the conventional method described above has the following drawbacks. That is, first, a parasitic pnp transistor formed by the p ⁺ source region 15 ₁ (or drain region 16 ₁ ), the n-type substrate 1 and the p- well region 5 and the n ⁺ type source region 15 ₂ (or drain region 16 ₂ ) The latch-up phenomenon occurs due to the generation of a parasitic npn transistor between the p-well region 5 and the n-type substrate 1. The latch-up phenomenon is determined by the resistance of the substrate 1 and the well region 5 and the probability of arrival of minority carriers. Since the probability of arrival is determined by the distance between the n-channel and p-channel device regions, miniaturization makes it easier for the latch-up phenomenon to occur, leading to deterioration in device characteristics. Furthermore, as shown in FIG. 1b, the p-well region 5 extends not only in the depth direction of the substrate 1 but also in the lateral direction (for example, if it extends 10 μm in the direction of the substrate, it also extends 7 to 8 μm in the lateral direction). This may lead to problems with integration and a decrease in the degree of integration. Furthermore,
As shown in FIGS. 1d and 1e, since ion implantation is performed to prevent field reversal of the n-channel and p-channel, the number of photolithography steps increases, which becomes an obstacle to improving productivity.

The present invention has been made to eliminate the above-mentioned drawbacks, and provides a method for manufacturing a high-performance, highly integrated complementary MOS semiconductor device in a simple process that prevents latch-up and miniaturizes elements. This is what I am trying to do.

The CMOS manufacturing method of the present invention will be explained below in Figure 2a.
This will be explained with reference to ~j.

[] First, a p-type silicon substrate 101 with a surface index of 100 is thermally oxidized in a wet oxygen atmosphere at 1000°C to form a thermal oxide film (insulating film) 1 with a thickness of 1 μm.
I grew 02. Next, a photoresist film is applied to the entire surface, and a resist pattern (mask material) covering the intended element area is formed by photolithography.
103a and 103b were formed. Continuing,
Using the resist patterns 103a and 103b as a mask, boron, which is an impurity for preventing inversion, is selectively ion-implanted into the substrate 101 through the thermal oxide film 102 under the conditions of an acceleration voltage of 210 KeV and a dose of 1×10 ¹³ cm ^-2 using, for example, double charge. A p ⁺ -type inversion prevention layer 104 was formed by heat treatment (as shown in FIG. 2a).

[] Next, for example, a 2000 Å thick layer of Al is applied to the entire surface.
The coating was vacuum deposited. At this time, as shown in FIG. 2b, due to the difference in level between the resist patterns 103a, 103b and the thermal oxide film 102, the same pattern 103
The Al coating 105 ₁ on the layers a and 103b and the Al coating 105 ₂ on the thermal oxide film 102 were discontinuous and separated. Next, resist pattern 103
a, 103b are removed and the Al coating 10 is formed thereon.
5 ₁ was lifted off, and the Al film 105 ₂ remained on the upper part of the thermal oxide film 102 in the intended element isolation region (as shown in FIG. 2c). Subsequently, using the remaining Al film ₁₀₅₂ as a mask, the thermal oxide film 102 was selectively etched by, for example, reactive ion etching to form an element isolation region 106. After that, the remaining Al coating 10 on the element isolation region 106
5 ₂ was removed (shown in Figure 2d). At this time, two adjacent island-shaped substrate regions 107 ₁ and 107 ₂ separated by the element isolation region 106 were formed.

[] Next, an oxide layer with a thickness of, for example, 1000 Å is grown on the exposed substrate regions 107 ₁ and 107 ₂ by thermal oxidation treatment, and then the oxide layer on one substrate region 107 ₁ is removed, and then the other substrate region 107 1 is grown. Area 107
₂ , a thin oxide layer 108 remained. Continuing,
A non-single crystal silicon layer, for example a polycrystalline silicon layer 109, having the same thickness as the element isolation region 106 was deposited over the entire surface. Continuing, polycrystalline silicon layer 10
9. The entire surface was irradiated with an energy beam, for example, a laser beam. At this time, as shown in Figure 2 f, p
The substrate 101 is crystallized from the side of the polycrystalline silicon layer that is in direct contact with the type silicon substrate 101 to form a single crystal, so that the entire p-type single crystal silicon layer 110 is formed.
It became.

[] Next, a plasma nitride film 111 was deposited on the entire surface of the single crystal silicon layer 110 (as shown in FIG. 2g). Subsequently, the plasma nitride film 111 was processed by reactive ion etching. At this time,
As shown in FIG. 2h, a single crystal silicon layer 110
The etching rate of the plasma nitride film deposited in the recesses is slower than that of the plasma nitride film deposited on the other flat silicon layer 110, and the plasma nitride film 111' remains only in the recesses of the single crystal silicon layer 110. did. Subsequently, the single crystal silicon layer is selectively etched using the remaining plasma nitride film 111' as a mask to form the element isolation region 1.
Island-shaped substrate regions 107 ₁ , 1 separated by 06
After leaving the p-type silicon layer only on ₀₇₂ ,
Using a resist pattern (not shown) as a mask, ions of, for example, phosphorus are implanted into the p-type single crystal silicon layer without the oxide layer 108 at the bottom under conditions of an acceleration voltage of 200 keV and a dose of 5×10 ¹¹ cm ^-2 , and heat treatment is performed at, for example, 1100°C. An oxide layer 108 exists at the interface between a p-type element region 112 made of a p-type single crystal silicon layer and the substrate 101, and an n-type element region (n-well region) made of a single crystal silicon region converted to an n-type. ) 113 (as shown in FIG. 2i).

[] Next, p-type and n-type element regions 112,
113 is thermally oxidized to grow an oxide film with a thickness of 400 Å, a phosphorus-doped polycrystalline silicon film is further deposited on the entire surface, and this is patterned to form each element region 1.
Gate electrodes 114 ₁ , 114 ₂ on 12 and 113
After selectively forming these gate electrodes 11
Gate oxide films 115 1 and 115 ₂ were formed by etching the oxide films using _{4 1} and 114 ₂ as masks. Next, arsenic is applied to the p-type element region 112.
Boron ions were implanted into the n-type element region 113 and heat treated to form n ⁺ -type source and drain regions 116 ₁ and 117 ₁ and p ⁺ -type source and drain regions 116 ₂ and 117 ₂ . After that, a CVD-SiO ₂ film 118 is deposited on the entire surface, contact holes 119 ₁ to 119 ₄ are opened, and then Al wirings 120 to 120 are formed by vapor deposition and patterning of an Al film.
A CMOS in which 123 was formed was manufactured (as shown in FIG. 2j).

Therefore, the product produced by the method of the present invention
In CMOS _, an element isolation region 106 is provided on a p-type silicon substrate ₁₀₁ as shown in FIG. p-type element region (n-channel Tr region) 112,
In addition to providing an n-type element region (p-channel Tr region) 113, the substrate 101 and the p-type element region 113 are
The structure has a thin oxide layer 108 interposed over the entire interface. Therefore, n-channel Tr and p
Since the channel Tr is insulated by the thin oxide layer 108, no parasitic transistor is formed, and a CMOS having good device characteristics without the latch-up phenomenon caused by this can be obtained. In addition, the element isolation region 106 and the p-type and n-type element regions 112 and 11
The surfaces of 3 and 3 are on the same level and can be flattened.
Furthermore, the n-type element region 113 serving as a well region is determined by the width between the element isolation regions 106, and lateral diffusion is prevented. Therefore, by preventing the latch-up phenomenon mentioned above, flattening the device area, and preventing lateral diffusion of the well area, high density and high integration can be realized.
You can get CMOS.

Furthermore, by providing the p ⁺ -type inversion prevention layer 104 under the element isolation region 106, the gap between the n-channel Tr formed in the substrate 101 and the p-type element isolation region 112 made of p-type single crystal silicon is increased. Malfunctions due to electrical leaks can be prevented.

In addition, as shown in FIG. 2i, the element isolation region 106
Element regions 112 and 113 made of p-type and n-type single-crystal silicon can be formed in the island-shaped substrate regions separated by , at substantially the same level as the surface of the element isolation region. Therefore, in the step [], oxide film growth,
After depositing the phosphorus-doped polycrystalline silicon film, it is possible to avoid the formation of resist residues at the edges of the element isolation region 106 during resist film application and photolithography, thereby making it possible to form a resist pattern with good dimensional accuracy. , and even a highly accurate gate electrode 11
4 ₁ , 114 ₂ can be formed. Furthermore, when forming the Al wiring in the same step [], it is possible to prevent each Al wiring 120, 123 from being cut off at the end of the element isolation region 106.

Furthermore, by forming the oxide layer 108 at the interface between the element region 112 of the n-channel Tr and the substrate 101, one step of forming the field inversion prevention layer (in this case, the step of forming the n ⁺ inversion prevention layer) can be omitted;
CMOS can be manufactured extremely easily and in mass production.

Furthermore, in the process of forming the element isolation region 106, bird's beaks do not occur as in the case of selective oxidation, so it is possible to suppress miniaturization of the element isolation region 106 and further reduce the dimensions of the element regions 112 and 113.
Highly integrated CMOS can be manufactured. Moreover, since white ribbons can be prevented from being generated in the element regions 112 and 113, excellent element characteristics can be achieved.
You can get CMOS.

In addition, as in the above embodiment, resist patterns 103a and 10
3b is formed, and using this as a mask, boron ions are implanted to form a p ⁺ type inversion prevention layer 104. After that, an Al film is evaporated and a resist pattern 10 is formed.
The element isolation region 106 and the inversion prevention layer 104 are formed by lifting off the Al film by removing the Al film 3a and 103b and etching the thermal oxide film ₁₀₂ using the remaining Al film 1052 as a mask to form the element isolation region 106. Self-alignment can be achieved, and ions can be prevented from leaking from the inversion prevention layer 104 to the source and drain regions formed in the element region.

In the above embodiments, a thermal oxide film is used as the insulating film, but the invention is not limited to this, and SiO ₂ films, Si ₃ N ₄ films, Al ₂ O ₃ films, etc. deposited by CVD may also be used.
Furthermore, amorphous silicon may be used instead of polycrystalline silicon as the non-single crystal silicon layer.

In the above embodiment, a laser beam is used as the energy beam, but an electron beam, an ion beam, etc. may also be used.

In the above embodiment, the ion implantation method was used as a means to change the p-type single crystal silicon layer to the n-type, but the method is not limited to this, and a method using a PSG film or AsSG film as a diffusion source, a phosphorus diffusion method, etc. can also be used. good.

In the above embodiment, an element isolation region is provided on a p-type substrate, a non-single-crystal silicon layer is coated, a p-type single-crystal silicon layer is formed by irradiation with an energy beam, and p-type single-crystal silicon is formed between the element isolation regions by selective etching. Although the p-type single-crystal silicon layer in which the oxide layer exists was converted to an n-type (n-well region) while leaving some layers, the present invention is not limited thereto. For example, a p-type single crystal silicon layer without an oxide layer may be changed to an n-type layer. Alternatively, using an n-type semiconductor substrate, one of the n-type single crystal silicon layers may be converted to a p-type (p-well region), contrary to the above.

In the above embodiment, an oxide layer was interposed on the entire interface between at least one of the element regions formed in two adjacent regions and the substrate, but a thin insulating layer such as an oxide layer was provided on a part of the interface. It is also possible to intervene. In such a case where the insulating layer is partially interposed, it is desirable to arrange the insulating layer at the interface portion close to the other adjacent element region side.

As described in detail above, according to the present invention, the latch-up phenomenon can be prevented and the elements can be miniaturized to achieve high performance.
It is possible to provide a method for manufacturing a highly integrated complementary MOS semiconductor device through simple steps.

[Brief explanation of the drawing]

1A to 1H are process sectional views showing conventional CMOS manufacturing, and FIGS. 2A to 2J are process sectional views showing CMOS manufacturing in an embodiment of the present invention. 101...P type silicon substrate, 102...Thermal oxide film (insulating film), 103a, 103b...Resist pattern, 104...P ⁺ type inversion prevention layer, 10
6...Element isolation region, 108...Oxide layer, 112
...Element region made of p-type single crystal silicon, 11
3...Element region made of n-type single crystal silicon, 1
14 ₁ , 114 ₂ ... gate electrode, 116 ₁ , 11
6 ₂ ... Source region, 117 ₁ , 117 ₂ ... Drain region, 120 to 123 ... Al wiring.

Claims (1)

[Claims] 1. A step of forming an insulating film to serve as an element isolation region on a semiconductor substrate of a first conductivity type, and ion-implanting impurities of a first conductivity type through the insulating film into a portion of the substrate where an element isolation region is to be formed to form a first conductivity type. a step of forming a high-concentration impurity layer of a type, a step of selectively etching away the insulating film to form an element isolation region on the substrate, and a plurality of island-shaped substrate regions separated by the element isolation region. forming an insulating layer sufficiently thinner than the element isolation region over the entire surface of at least one of the two adjacent regions, and depositing a non-single crystal silicon layer over the entire surface, and then applying an energy beam to the non-single crystal silicon layer. The silicon layer is irradiated to single-crystallize the non-single-crystal silicon layer that is in direct contact with the island-like substrate region not covered with the thin insulating layer, using the substrate as a seed crystal, and the island-like region covered with the insulating layer is A step of also monocrystallizing the non-single-crystal silicon layer on the substrate region and etching the single-crystal silicon layer results in an island-like substrate region covered with the insulating layer and another island-like substrate region adjacent thereto. After leaving a single crystal silicon layer whose surface is at the same level or almost the same level as the element isolation region, one of these single crystal silicon layers is doped with an impurity of the second conductivity type to form at least an adjacent island-like layer. 1. A method for manufacturing a complementary MOS semiconductor device, comprising the step of forming element regions of a first conductivity type and a second conductivity type in a substrate region.