JPH03241445A - Pipeline system - Google Patents

Abstract

PURPOSE:To prevent a memory write operation delayed by fetching a check bit generation circuit into a pipeline, generating a check bit in parallel with the transfer of write data to a write data register, and sending the write data to a memory at the same timing. CONSTITUTION:A check bit generation circuit 5 for soft error correction, and a check bit storage register 3 which stores the check bit of the circuit are provided, and the input of the check bit generation circuit 5 for software error correction is connected to an internal bus 2. The execution of a store instruction is performed by outputting data in a general register 1 to the internal bus 2 first, and transferring it to the write data register 4 via the internal bus 2, and performing a write operation on an external memory 6 at the next machine cycle. The check bit of the write data is prepared together with which realizes fast memory write.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a pipeline system, and in particular, to a pipeline system, a check bit for correcting a 1-bit error (soft error) that occurs during memory access is provided. This paper relates to a pipeline system in which a generation circuit is inserted.

[Conventional technology]

In the conventional technology, a check bit generation circuit for soft error correction is located between a processor and a memory, and generates check bits from data output from the processor and writes them into the memory.

[Problem to be solved by the invention]

In the conventional technology described above, in which check bits are generated from the data output by the processor and written to memory, the time to generate the check bits is included in the memory cycle time, which causes problems such as interleaving. This has been a major problem in terms of performance in small-scale equipment that cannot utilize the technology.

[Means to solve the problem]

The structure of the pipeline system of the present invention is such that when processing a store instruction, data stored in the general register is transferred to the write data register via an internal bus, and a write operation to the memory is performed in the next machine cycle. In a line type one-chip processor, a first means for generating a check bit for error correction as an input of write data being transferred on the internal bus; and a check bit generated by the first means; a second means for holding the bit at the same timing as the timing at which data on the internal bus is stored in the write data register; The feature is that the check bit is output to the memory.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 shows a block diagram of an embodiment of the present invention. In the figure,
1 is a general register, 2 is an internal bus, 4 is a write data register, 6 is an external memory, 5 is a check bit generation circuit for soft error correction, which is a feature of this embodiment, and 3 is the check bit. This is a check bit storage register that stores . The input of the soft error correction check bit generation circuit 5 is connected to the internal bus 2.

To execute a store instruction, first, the data in general register 1 is output to internal bus 2, transferred to write data register 4 via internal bus 2, and a write operation is performed to external memory 6 in the next machine cycle. be exposed.

In this embodiment, check bits are generated along the flow of the write data. In other words, during the period when write data is transferred from general register 1 to write data register 4, the software
A check bit is generated by the error correction check bit generation circuit 5, and is stored in the register 3 at the same time as the write data is stored in the write data register 4. Furthermore, during a period in which a write operation is performed to the external memory 6, a check bit is also output at the same timing as data is output to the memory.

Details of the check bit generation circuit 5 for soft error correction are omitted here because the check bit generation circuit itself is already common and has no bearing on the scope of the claims of the present invention.

As the most effective example of this embodiment, FIG. 2 shows a timing chart when store instructions are processed successively.

This example assumes a pipeline system, so 1
Instruction processing is divided into the following processes, and the number of pipeline stages is three. Each process basically ends in one clock, and instruction decode D, address calculation A, address conversion T, operand read O2 operation E, and result storage W each form one stage of the pipeline. , one stage of the pipeline is to be completed in two clocks. Memory access can be performed in one clock, and instruction fetch is performed when there is no operand read/write operation6 D=Instruction decode A Near address calculation T Near address conversion O: Operand read Store instruction Then I won't do anything.

E: Arithmetic W Nilight (result storage) Result storage is usually for the neural register and memory Yes, but with the store command is for memory. Ru.

Here, the process of transferring write data from the general register 1 to the write data register 4 is performed in the E stage, and the write operation to the external memory 6 is performed in the W stage.

Therefore, according to this embodiment, the check bit of the write data is prepared together with the write data at the end of the E stage, and is supplied to the memory at the same timing as the write data in the next W stage. Therefore, the time required to generate a check bit is not included in the W stage included in the E stage, so high-speed memory writing is possible in the W stage, the vibe line is not disturbed, and subsequent instructions are Processed without waiting.

Since it is a pipeline system, the processing of each stage described above is required to be completed within the same predetermined time (two clocks in FIG. 2). However, this requirement is the strictest in the 0 stage and the W stage, that is, the stages in which memory access is performed.

In particular, in the W stage, when it is necessary to generate check bits for soft error correction when writing data to memory, the time required to generate the check bits is added to the processing time of the W stage. It is inevitable that the processing cannot be completed within one machine cycle and that only the W stage will be doubled, for example.

Recently, with the advent of high-speed SRAM, memory access has become
This can now be done using a clock, which greatly improves performance. Here, if the processing time of the W stage is longer than that of the other stages, the instructions subsequent to the write instruction will be forced to wait in the previous stage, as shown in FIG.

〔Effect of the invention〕

As explained above, the present invention incorporates a check bit generation circuit for soft error correction into the vibe line, and generates a check bit in parallel with transferring write data from the general register to the write data register. By sending the data to the memory at the same timing as the write data, it eliminates delays in memory write operations due to the time it takes to generate check bits, greatly contributing to improved performance.

On the other hand, the soft error correction function (ECC function) is essential for equipment that requires high reliability.
In recent years, it has also been commonly adopted in small-scale devices using SRAM. If the ECC function is provided between the processor and the memory, as described in this embodiment, the memory cycle time will increase and the performance will decrease, but the present invention solves this gap between reliability and performance. It completely overcomes the

1...General register, 2...Internal bus, 3.
. . . Register for storing check bits, 4 . . . Register for storing write data, 5 . . . Check bit generation circuit for soft error correction, 6 . . . External memory.

Claims (1)

[Claims] In store instruction processing, the data stored in the general register is transferred to the write data via the internal bus.
In a pipelined one-chip processor that transfers data to a register and performs a write operation to memory in the next machine cycle, a check bit for error correction is generated as input for write data being transferred on the internal bus. and second means for holding the check bit generated by the first means at the same timing as when data on the internal bus is stored in the write data register. , A pipeline method characterized by outputting a check bit to the memory at the same timing as the data when writing data to the memory in a store instruction.