JPH03241596A - Semiconductor storage device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to semiconductor memory devices, and in particular to electrically erasing and erasing devices.
The present invention relates to a writable non-volatile memory device (EEPROM).

[Prior Art] In recent years, semiconductor memory devices have been using error detection and correction (error detection and correction) to prevent malfunctions caused by soft errors associated with higher integration, or cell destruction caused by repeated data writing/erasing due to the cell structure.
Error Checking and Cor
Increasingly, devices are equipped with a so-called ECC circuit having a recting (hereinafter referred to as "ECCJ") function on the same semiconductor substrate.

FIG. 4 is a block diagram showing one embodiment of such a conventional EEPROM, FIG. 5 is a cross-sectional structural diagram of the memory cell shown in FIG. 4, and FIG.
7 is a characteristic diagram showing the relationship between the gate voltage and drain current of the OM, FIG. 7 is a logic diagram of the test bit generation circuit shown in FIG. 4, and FIG. 8 is a logic diagram of the check bit generation circuit shown in FIG. FIG. 2 is a logic diagram of a circuit.

The configuration will be described below with reference to these figures.

The memory cell array 1 consists of a main data storage memory cell area 1a and a test data storage memory cell area 1b. Input signal X. -Xn is detected, waveform-shaped and amplified by the X address buffer 2, and the X decoder 3 that receives this selects a predetermined word line 106 of the main data storage memory cell array 1a. Input signal Y. -Ym is detected, waveform-shaped, and amplified by the Y address buffer 4, and the Y decoder 5 receives the signal and transfers it to a predetermined bit line 1 of the main data storage memory cell array 1a via the Y data 8 circuit 6.
07 is selected. Data pin 7 where data is input/output
Data Do to D7 inputted from the input buffer 8 are detected, waveform-shaped, and amplified by the input buffer 8, and transmitted to the bit line 107 of the main data storage memory cell array 1a via the Y-data 8 circuit 6, and then sent to the column latch high voltage switch 18. latched to.

The test bit generation circuit 9 tests the data output from the input buffer 8 and generates 4-bit test bit data P1 to
Generate P4. Generated inspection bit data P1 to P
4 is transmitted to the bit line of the test data storage memory cell array 1b via the Y-day 8 circuit 6 and latched by the column latch high voltage switch 18. The sense amplifier 10 is
Memory cell area 1 read out via Y-day 8 circuit 6
Detect and amplify data within. The ECC circuit 11 inspects the data read out via the sense amplifier 10, and if a 1-bit failure occurs, it automatically detects the error and corrects the data. Data outputted from the ECC circuit 11 is outputted to the outside from the data pin 7 via the output buffer 12. A circuit consisting of a control signal buffer 13, a read/write control circuit 14, an erase/program control circuit 15, a high voltage generation circuit 16, and a continuous output control circuit 17 receives a chip enable signal τ1, an output enable signal ゛σ
1 and the write enable signal WE, etc., performs control to read/write/output data in the memory cell array 1 and to place the chip itself in an operating state/standby state. The column latch high voltage switch 18 latches input data DO to D7 and test bit data P1 to P4 as described above, and also connects them to the bit line 107 during programming and to the control gate 108 during erasing.
Apply high voltage to. Memory cell 101 is composed of selection transistor 102 and memory transistor 103. The impurity region 104 is the memory transistor 1
03 and the source region of the selection transistor 102, and the impurity regions 104 and 1
07 forms the source/drain regions of the selection transistor 102. Impurity region 104 and impurity region 1
A gate electrode 106 is formed above the semiconductor substrate 111, which serves as a channel region between 07 and 07, and is connected to the word line shown in FIG. The impurity region 104 and the impurity region 110 constitute the source/drain region of the memory transistor, and a floating gate 105 is formed above the semiconductor substrate 111 which becomes the channel region of these regions via an insulating film. A control electrode 108 is formed above the floating gate 105 with an insulating film interposed therebetween.

As shown in FIG.
The 12 transistors o-MD, MP, .about.MP are lined up, and the control gate transistor 109 is added to form one byte (see the broken line). In Figure 4, the symbol D
Bit lines 10 designated O-D7 and P1-P4
7 are bit lines BLI to BL12. Each circuit 121 to 124 in FIG. 8 constitutes the ECC circuit 11, and includes an exclusive OR circuit (rEXOR circuit) 121 for checking input bits and check bits, an inverter 122, and an OR circuit. (hereinafter referred to as "rAND circuit") and EXO for correcting bit errors.
This is the R circuit 124.

Next, the operation of the EFROM will be explained in the following order.

■ Erasing and programming operations in memory cells ■ Writing operations of data ■ Reading operations of data ■ Erasing and programming operations in memory cells The memory cell 101 has a configuration as shown in FIG. The gate 103 has a double structure covered with an insulating layer (not shown). A high positive voltage is then applied to the control gate 108, drain diffusion region 104, source diffusion region 110 and P
The potential of the type semiconductor substrate 111 is set to zero. A part of the insulating layer where the floating gate 105 faces the region 104 which is the drain region of the memory transistor 103 and the source region of the selection transistor 102 is formed of a very thin oxide film, that is, a tunnel oxide film 109. Through this tunnel oxide film 109, electrons are tunneled between the floating gate 105 and the drain region 104, and electrons are exchanged with each other. By accumulating positive or negative charges in the floating gate 105, the threshold voltage of the memory transistor 103 is changed, and binary data of "0" or "1" is stored.

FIG. 6 is a diagram showing the gate voltage/drain current characteristics of a conventional EEFROM.

In the figure, the horizontal axis represents the gate voltage of the control gate, and the vertical axis represents the drain current generated between the drain diffusion region and the source diffusion region. The figure shows the characteristics when the voltage of the drain diffusion region is set to 1V. A straight line 60 indicates a state in which a write operation has been performed, and the floating gate 2 is in a state of being depleted of electrons so that it is in a depression type state. Its threshold is 4V
It is. On the other hand, the straight line 64 is in the state where the erase operation has been performed and electrons are injected into the floating gate, so it is an enhancement type. Its threshold is 4v.

Therefore, the presence or absence of data storage can be detected by applying OV to the control gate at the time of reading and based on the sense level 15en which is the drain current at that time. That is, the drain current is at the sense level l5en
If the flow exceeds "0°l5en," it is assumed that the information is "1" and the storage device can be determined by the sense amplifier.

In other words, the erase operation means that the floating gate 105
This refers to injecting electrons into the memory transistor 103 to shift the threshold voltage of the memory transistor 103 to a higher side and store data "1#." Specifically, with the bit line 107 at ground potential, the word line 106 and the control gate line This is done by applying a high voltage to 108.

The programming operation refers to pulling out electrons from the floating gate 105 to shift the threshold voltage of the memory transistor 103 to a lower side, and storing data "0". Specifically, the control gate 108 is set to the ground potential. This is done by setting the word line 106 and bit line 107 to a high potential.

■ Data writing operation First, when the “L” level signal is input as the signal ■ and WE, the control circuit, that is, the control signal buffer 13
, read/write control circuit 14, erase/program control circuit 15, and high voltage generation circuit 16 are activated. X address signal X. -Xn selects a predetermined word line 106 via the X address buffer 2 and the X decoder 3;
Y address signal Y. -Ym selects a predetermined bit line via Y address buffer 4, Y decoder 5 and Y data 8 circuit 6. Then, when the data DO~D7 are input through the eight data bins 7, the data DO~D7 are inputted via the eight data bins 7.
7 is transmitted to the bit line 107 of the main data storage memory cell array 1a via the input buffer 8 and the Y data 8 circuit 6, and is latched by the column latch high voltage switch 18. On the other hand, the output of the input buffer 8 is also input to the test bit generation circuit 9, where the 4-bit test bit data P
1 to P4 are generated. The test bit data P1 to P4 are transmitted to the bit line 107 of the test data storage memory cell array 1b via the Y-day 8 circuit 6, and latched by the column latch high voltage switch 18. Here, as a method of generating test bit data P1 to P4 from input data DO to D7, for example, 4 or 5 of the 8 signal lines inputting data DO to D7 as shown in FIG. EX that takes out the signal lines of the book and connects them to those signal lines
The OR circuit 91 generates test and cut data. For example, input data DO to D7 are sequentially (0, 1, 0, 1, 0
, 1, 0, 1,), then the check bit data P
1 to P4 become (0°1.1.1) in order.

When address and data latching is completed, a high voltage is supplied to column latch high voltage switch 18 and word line high voltage switch 19, and memory cell area 1 is activated. Then, predetermined data is written into a predetermined memory cell transistor according to the procedure for erasing/programming the memory cell. A series of these flowcharts is shown in FIG.

In FIG. 10, first in step Sll, data is written from the outside into the device as an external write cycle. However, the written data is not written into a memory cell, but is taken into a column latch provided on each bit line and control gate line.

Next, in step S12, as an internal write cycle,
A high voltage pulse is generated internally, and the cycle moves to writing the data latched in the column latch to the memory cell. The specific contents of the internal write cycle are steps S13 and S14.
is shown.

In step S13, as an erase cycle, the byte to be rewritten is erased, that is, an operation of writing "1" is performed.

In step S14, as a program cycle,
An operation of programming a cell whose input data should be "0", that is, an operation of writing "0" is performed.

■Data read operation First, when the signal is set to 1 and δ and the "L" level is input, the control circuits, that is, the control signal buffer 13, the read/write control circuit 14, and the read control circuit 17 are activated, and the sense Amplifier 10 and output buffer 12 are activated. and X address buffer 2 and X decoder 3
word line 1 according to the input X address signal.
06 is selected, and then a predetermined bit line 107 is selected by the Y address signal inputted via the Y address buffer 4, Y decoder 5, and Y gate circuit 6. As a result, the desired data D of the memory transistor
O to D7 and P1 to P4 are connected to bit line 107 and Y
After being amplified by the sense amplifier 10 via the gate circuit 6, the signal is input to the FCC circuit 11. That is, data DO
~D7 and P1 to P4 are the same combination as selected by the check bit generation circuit 9 at the time of writing, and are first output to EXOR121.
is input. However, the inspection bit data P1 to P4
are the corresponding human data (for example, data P1
In the case of DO, DI, D2. Since the number of "1"s in D3) is predetermined to be an even number, if there is no failure in the memory transistor 103, the EXOR circuit 1
21, all outputs M1 to M4 of one side become "L° level" and are inverted outputs M1 to M4 through the other inverter 122.
are all "H level. Then, the AND circuit 1 of the next stage
All the outputs of the memory transistors 103 become 'L' level, and in the end all the outputs DOa to D7a of the EXOR circuit 124 at the final stage are outputted as input data DO-D7.Next, one of the memory transistors 103 Broken down, 1
Consider a case where a bit (for example, data D3) that should originally be "1" is input as "O". Then, the input data of EXORI of the EXOR circuit 121 becomes (0, 1, 0, 0, O), the input data of EXOR4 becomes (1, O, 0, 1, 1), and the output "and M4 are both "H". " level, and outputs M1 and M4 both become "L" level. Since data D3 is not input to outputs M2 and M3, both become "L2 level." When the output of the AND circuit 12B is at the "L" level, the output of the EXOR circuit 124 at the next stage is at the same phase level as the other input signal, that is, DO-D7.

In this example, excluding AND4 of the AND circuit 123,
Since the outputs of all the AND circuits 123 are "L level", the input data DO-D2 and D4-D7 are output as they are as the outputs DOa-D2a and D4a-D7a.

On the other hand, as the output D3a, AND4 of the AND circuit 123
Although the output of EX is at “H” level.

This data is the inverted version of the other data D3 inputted manually by R8. In this way, the data D3 of the failed memory transistor is detected and corrected by the ECC circuit 11, and the same data D3 as inputted through the output buffer circuit 12 is detected and corrected by the ECC circuit 11.
O to D7 are output from the data bin 7. In addition, in the above explanation, the data DO~D written in the memory cell array 1
Although the example in which a bit error occurs in D3 among the 12 bits of data DO to D7 and P1 to P4 is shown, the same result will occur even if a bit error occurs in any other data among data DO to D7 and P1 to P4. The error is detected and corrected, and the ECC circuit 1
Normal data is output from 1.

Here, the types of EEFROM failures (defectives) will be explained. One type of failure is when the memory transistor 103 fails, as described above, and another type of failure is when the selection transistor 102 fails. If the memory transistor 103 fails, for example, even if a memory transistor in an MD fails, writing/reading will not affect other memory transistors, and the problem will be limited to the bit that has the failed memory transistor. becomes.

- Consider the case where the force selection transistor 102 fails.

The cause of the failure is that the word line 106, which is at a high voltage during both erasing and programming, serves as the gate of the selection transistor, so this high voltage destroys the gate oxide film and shorts it to the bit line 107. That is most likely.

In this case, in the erase cycle, the word line 106 is at a high voltage and the bit line 107 is at a ground potential. Therefore, if the gate oxide film of the selection transistor 102 is destroyed and the gate and drain are short-circuited, the word line 106, which should be at high voltage, and the bit line 10, which should be at ground potential.
7 will be shorted. As a result, no high voltage is applied to the word line 106 and no high voltage is applied to the gate of the memory transistor 103, that is, the control gate 108. This means that all memory transistors within a byte and all memory transistors on the same word line become non-erasable.

[Problems to be Solved by the Invention] In the conventional EEPROM as described above, when a memory transistor fails, it is possible to detect this failure by employing an FCC circuit, correct the error, and output. If a fault occurs in the byte, not everything in that byte is erased, and even if an FCC circuit is employed, it is impossible to detect all faults, correct errors, and output. Therefore, an EEPROM in which a selection transistor has failed cannot be shipped as a product, resulting in a decrease in product yield.

The present invention was made to solve the above-mentioned problems, and aims to improve product reliability and yield even if a word line failure occurs in an EEFROM.

[Means for Solving the Problems] A semiconductor memory device according to the present invention includes a first memory cell connected to a corresponding memory cell and held at a potential higher than a first potential to write information into the corresponding memory cell. A second word line is connected to a word line and a corresponding memory cell, and is held at a potential higher than the first potential to write information into the corresponding memory cell; a potential applying means for applying a second potential; a detecting means for detecting that the potential appearing on the first word line is less than the first potential by the applied second potential; and control means for controlling the potential application means so as to apply the second potential to the second word line instead of the first word line.

[Function] In the present invention, the high voltage level of a word line is detected, and when the level falls below a predetermined level, when that word line is selected, the selection is switched to a spare word line.

[Embodiment] FIG. 1 is a block diagram of the periphery of the memory cell array of an EEPROM according to an embodiment of the present invention, and the same symbols as those of the EEFROM shown as a conventional example in FIG. It shows the part. In addition,
Peripheral circuits not shown in FIG. 1 are the same as those shown in FIG. 4.

The configuration will be explained below with reference to the drawings.

The memory cell areas include a main data storage memory cell area 1a and a test data storage memory cell area 1b.
A spare memory cell area 31 is formed around the area. The structure of the spare memory cell area 31 itself is similar to the main data storage memory cell area 1a and the test data storage memory cell area 1b. A spare X decoder 33 is connected to the spare memory cell area 31 via a word line 206.
is formed. On the other hand, the output from the erase/program control circuit 15 is input to the high voltage generation circuit 16 and also to the reference voltage generation circuit 34, where the high voltage reference value vP
P is generated. High voltage reference value VPP is comparator 3
6 and the address replacement EEPROM 37. The comparator 36 includes a word line 106 and a word line 2 connected to the X decoder 3 and the spare X decoder 33.
Branches from 06 are connected. The output of the comparator 36 is input to an EEPROM 37 for address replacement.

The address signal branched from the output from the X address buffer to the X decoder 3 is input to the address replacement EEFROM 37. EEPROM37 for address replacement
The output of is input to the X decoder 3 and the spare X decoder 33.

FIG. 3 is a circuit diagram showing a specific configuration of the main circuit portions shown in the block diagram of FIG. 1.

Next, the write operation will be explained with reference to FIG. 1 and FIGS. 2 and 3 showing flowcharts of the write operation.

First, data is written to the device from the outside as an external write cycle. However, the written data is not written into the memory cell, but is taken into the column latch provided on each bit line and control gate line (Sl
).

Next, when "L" level signals are input as signals CE and WE, the address and data latching is completed.

That is, from step S2 onwards, as an internal write cycle, a high voltage pulse is generated internally and the data latched in the column latch is written into the memory cell. The specific contents of this internal write cycle are from steps 83 to S5.
is shown.

A high voltage reference value KVPP is generated in a reference voltage generation circuit 34 in response to a signal from the erase/program control circuit 15 and is applied to a comparator 36 .

On the other hand, based on the X address signal, the word line drive signal
~X, is generated and a predetermined word line WL is selected.

Then, in order to apply a high voltage to the word line WL, a high voltage is applied via the column latch high voltage switch 18. The potential VPP appearing on the word line is compared with the reference value KVPP in the comparator 36 when the signal A becomes "H" level. By comparing, for example, vP
When P>KVPP, that is, when there is no leakage in the word line WL, the node N becomes "H° level. Then,
Since the potentials of the drain regions of memory transistors M1 and M2 of address replacement EEPROM 37 are at the "H" level, no writing is performed to these transistors M1 and M2. Therefore, transistors M1 and M2 are both turned on, and the address replacement EEF
The output signal 11 of the ROM 37 becomes "H rubel".

As a result, the output of spare
4). Then, in step S5, as a program cycle, a program operation is performed on a cell whose input data should be "0".

That is, "0" is written into that cell, and the write operation is completed.

On the other hand, in the high voltage pulse comparison cycle of step S3, for example, if the potential of the high voltage applied to the word line 106 is equal to or lower than the high voltage reference value KVPP, there is a failure on the word line 106, that is, a failure in some selection transistor 102. It is determined that the memory transistor on the word line 106 cannot be erased, and the word line is replaced. In this case, the comparison result of the comparator 36 becomes VPP<KVPP, so the node N1 goes to "L" level.Then, the high voltage reference value KVPP is boosted based on the oscillation signal Rφ from the oscillator, and data is written to the memory transistors M1 and M2. is carried out. Therefore,
The threshold voltages of transistors M1 and M2 are shifted to the enhancement side, and these transistors are both turned off.

And this state will continue from now on. As a result, the output signal π1 of the address replacement EEPROM 37 is “L”
Level, spare X decoder drive signal RXi is drive signal
Select and output either i or Xi. In this embodiment, Xi corresponds to X2 to X5. That is, four types of word line drive signals are handled as one block, and word lines are replaced. The output of the spare X decoder 33 to the word line 206 is
The signal becomes "H" level, and the replacement control signal NEN becomes "L" level. Since the signal NEN is input to the X decoder 3,
The word line WL that is considered to have leaked is thereafter unselected, and the word line is replaced. That is, when a defective address is selected via the X address buffer 2, the content that deselects the X decoder for the defective address and activates the spare X decoder is stored in the EEPROM 37.
is memorized. In this way, the replacement of the defective word line with a good word line is completed (S3). Thereafter, the normal erase cycle (S4) and program cycle (S5) are similarly performed to complete the write operation.

In the read cycle, the output signal from the X address buffer is sent to the EE for address replacement in parallel with the X decoder 3.
It is input to FROM37. Since the memory transistors M1 and M2 of the EEFROM 37 store the above-mentioned contents, the X decoder 3 corresponding to the defective address becomes unselected, the spare X decoder 33 is activated, and the word line of the spare memory cell array is selected and the correct address is selected. Data is read.

Note that in the above embodiment, an EEPROM with an ECC circuit is used.
However, it can also be applied to an EFROM equipped with an ECC circuit.

Further, although the above embodiment is applied to EEF ROM, the idea of the present invention can be similarly applied to DRAM and SRAM.

Further, although the above embodiment deals with a word line failure, it goes without saying that the idea of the present invention can be similarly applied to a bit line failure.

[Effects of the Invention] As explained above, the present invention selects a spare word line to read/write data when a word line is defective, thereby improving the yield of EEFROM.
Improve reliability in read and write operations.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an EEFROM according to an embodiment of the present invention, and FIG. 2 is a block diagram of an EEPRO according to an embodiment of the present invention.
FIG. 3 is a circuit diagram showing the specific configuration of the main circuit parts shown in the block diagram of FIG. 1, FIG. 4 is a block diagram of a conventional EEFROM, Figure 5 is a cross-sectional structural diagram of a general EEFROM memory cell.
Figure 6 is a diagram showing the characteristics of the gate voltage and drain current of the EEFROM in Figure 5, and Figure 7 is a diagram showing the characteristics of the EEFROM in Figure 4.
FIG. 8 is a diagram showing the specific contents of the error detection and correction circuit in FIG. 4, and FIG. 9 is a diagram of the general E.
FIG. 10 is a block diagram of a memory cell area of an EPROM, and is a flowchart showing the contents of a write operation of a conventional EEPROM. In the figure, 1 is a memory cell area, 1a is a memory cell area for storing main data, 1b is a memory cell area for storing test data, 31 is a spare memory cell area, 2 is an X address buffer, 3 is an X decoder, and 34 is a memory cell area for storing test data. Reference voltage generation circuit, 36 is a comparator, 37 is EEP for address replacement
ROM, 33 is a spare X decoder, 106 is a word line,
206 is a spare word line. Note that the same reference numerals in each figure indicate the same or corresponding parts.

Claims (1)

[Scope of Claims] A first word line that is connected to a corresponding memory cell and writes information to the corresponding memory cell by being held at a first potential or higher; a second word line that writes information into the corresponding memory cell by being held at a potential higher than the first potential; potential applying means that applies a second potential to the first word line; a detection means for detecting that the potential appearing on the first word line is less than the first potential by a second potential applied to the first word line; and control means for controlling the potential application means to apply the second potential to the second word line instead of the second word line.