JPH03245578A - Semiconductor device - Google Patents

Abstract

PURPOSE:To restrain an IGFET from fluctuating in threshold voltage without making it large in size by a method wherein a photoelectric transducer which generates an output to cut off the IGFET is provided onto the IGFET. CONSTITUTION:A photoelectric transducer 3 composed of photoelectric conversion layers 17 formed on an IGFET 2 generates an output to cut off the IGFET 2 through an optical input L. By this constitution, as the photoelectric transducer 3 keeps on applying a negative (positive) voltage between a gate and a source while the optical input L is inputted, a threshold voltage is shifted to a negative (positive) voltage, and as the stored charge on a load applies a positive (negative) voltage between a drain and a gate while the optical input L is turned OFF, a threshold voltage shifted to a negative (positive) is made to recover its initial value. Therefore, as a threshold voltage is kept in a range of value close to the initial value without varying much, a semiconductor device of this design can display a normal function through a long term.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to an optical input type semiconductor device.

[Conventional technology]

Conventionally, there is an optical input type semiconductor device having an equivalent circuit shown in FIG.

In this semiconductor device, an insulated gate field effect transistor 91 is connected in parallel to a photoelectric conversion element 90 that receives optical input and generates an electromotive force (output). The element 90 is cut off while light is being input to the element 90, and becomes conductive when the light input disappears and the output disappears.

When light is input, a reverse bias voltage is generated in the resistance element 92 due to the current flowing through the stray capacitance C on the load side connected between the output terminals 95 and 96, and a reverse bias voltage is applied between the gate and the source, so that the transistor 91 is cut off. When the optical input disappears, a forward bias voltage due to the charge accumulated in the stray capacitance C is applied between the gate and the source via the resistance element 93, so that the transistor 91 becomes conductive and the charge accumulated and remaining in the stray capacitance C is discharged.

[Problem to be solved by the invention]

However, the above semiconductor device has a problem in that the threshold voltage of the insulated gate field effect transistor 91 changes significantly. For example, as shown in FIG. 5, this insulated gate field effect transistor 91 has a semiconductor layer (
A gate electrode 83 is provided below an amorphous silicon layer 81 via an insulating layer 82, and a source electrode 84 and a drain electrode 85 are provided above the semiconductor layer 81. The semiconductor layer 81 has a low impurity concentration (
For example, it consists of an i-type semiconductor layer) 81a and a relatively high impurity concentration layer (for example, an n-type semiconductor layer) 81b.

If a positive voltage is continued to be applied to the gate electrode 83, it will change in the downward direction as shown by curve A in FIG. 6, and if a negative voltage is continued to be applied, as shown by the curved line in FIG. Change in one direction. The insulating layer 82 is usually a 5iIN4 layer formed using a plasma CVD method or the like;
The layer has many trap levels due to defects, etc., and if a voltage of the same polarity is applied for a long time, charges will be trapped, and this will cause the threshold voltage to change significantly.

In conventional semiconductor devices, the application time of the reverse bias voltage is extremely short compared to the application time of the forward bias voltage, and in fact,
Since only the forward bias voltage is applied, the threshold voltage of the transistor 91 changes significantly.

When the threshold voltage of transistor 91 changes, the discharge time becomes longer. When a power field effect transistor is driven by the output of this semiconductor device, an inconvenience arises in that the off time becomes long.

On the other hand, miniaturization (high integration) of semiconductor devices is one of the most important issues. Even if the change in the threshold voltage can be prevented, the practicality is low if the device becomes larger.

In view of the above circumstances, it is an object of the present invention to provide a semiconductor device that can suppress changes in the threshold voltage of an insulated gate field effect transistor without increasing the size of the device.

[Means to solve the problem]

In order to solve the above problem, in the invention according to claim 1, for example, as shown in the equivalent circuit shown in FIG. A semiconductor device comprising insulated gate field effect transistors 2 connected in parallel, the insulated gate field effect transistors 2 being cut off during the output of the first photoelectric conversion element 1 and turned on when the output disappears. In the device, a second photoelectric conversion element 3 generates an output for blocking the insulated gate field effect transistor 2 upon receiving the light;
For example, as shown in FIG. 1, the second photoelectric conversion element 3 has a structure that is composed of a plurality of photoelectric conversion layers 17 and provided on the insulated gate field effect transistor 2. I try to take it.

Usually, as in claim 2, a second photoelectric conversion element 3 and a resistance element 4 connected in series to the second photoelectric conversion element 3 are connected in parallel to the insulated gate field effect transistor 2, and the second photoelectric conversion element 3 is connected in parallel to the insulated gate field effect transistor 2. The structure is such that the midpoint between the element 3 and the resistor element 4 is connected to the gate electrode G of the insulated gate field effect transistor 2.

Specifically, the structure around the insulated gate field effect transistor 2 and the second photoelectric conversion element 3 is as shown in FIG. 1 or 2.

In the case of FIG. 1, an insulated gate field effect transistor 2 is formed on an insulating substrate 10. In the case of FIG. That is, a semiconductor layer with a high impurity concentration (for example, an i-type semiconductor layer) 12a having a channel region and a semiconductor layer with a high impurity concentration (for example,
A semiconductor layer 12 in which n-type semiconductor layer) 12b is stacked except for the channel region is provided on an insulating substrate 10, and a drain electrode 13 and a source electrode 14 made of AI or the like are provided in the semiconductor layer 12b with a high impurity concentration. At the same time, a gate electrode 15 made of Cr or the like is provided with an insulating layer (for example, Si, N4 layer) 16 interposed therebetween. The semiconductor IW12 is formed of, for example, an amorphous silicon thin film. In this way (as in claim 3), when the gate electrode 15 is provided on the insulating layer 16 laminated on the semiconductor layer 12, the gate electrode 15 is formed simultaneously with the formation of the first photoelectric conversion element 1. Since the transistor 2 can be built in, there is an advantage that manufacturing is easy.

The photoelectric conversion element 3 provided on the insulated gate field effect transistor 2 has a configuration in which the gate electrode 15 is the lower electrode and three photoelectric conversion elements M11 are provided between the transparent electrodes (for example, an Ingot layer) 18. It has become. Each photoelectric conversion layer 17 is formed of, for example, amorphous silicon, and includes a first conductivity type (for example, n-type) semiconductor layer 17a, a low impurity concentration layer for photoelectric conversion thin film (for example, i-type semiconductor layer) 17
b.

The structure is such that second conductivity type (for example, p-type) semiconductor layers 17c are sequentially stacked. It goes without saying that the number of photoelectric conversion layers 17 is not limited to three, and two or more of the required number may be laminated. Note that the transparent electrode 18 is the source electrode 1
4 by wiring not shown.

In the case of Fig. 2, the insulated gate field effect transistor 2
The configuration is as follows. That is, an insulating layer (for example, St) is formed on a gate electrode 15' made of Cr or the like formed on the surface of the insulating substrate 10.

N4 layer) 16' is provided, on which a semiconductor layer with a high impurity concentration (for example, an n-type semiconductor layer' A semiconductor layer 12' in which I 12b' is stacked except for the channel region is provided, and a drain electrode 1 of Af or the like is provided on the semiconductor layer 12b' with a high impurity concentration.
3' and a source electrode 14' are provided. semiconductor layer 1
2' is formed of, for example, an amorphous silicon thin film. In this way (as in claim 4), the gate electrode 15'
However, the insulating layer 16' on which the semiconductor layer 12' is laminated is formed.
In the case of a structure in which the semiconductor layer 12' is provided in advance on the lower side of the semiconductor layer 12', there is an advantage that it becomes easier to form a high-quality semiconductor layer 12'.

The photoelectric conversion element 3 provided on the insulated gate field effect transistor 2 is connected to a lower electrode 19 of Cr or the like formed through an insulator 111 of Sing or the like and a transparent electrode (for example, I
The structure includes three photoelectric conversion layers 17'... between nl Os l1i) 1 B'.

Each photoelectric conversion N17' is made of, for example, amorphous silicon, and has a second conductivity type (for example, p-type) semiconductor layer 17a.
', a low impurity concentration layer for a photoelectric conversion thin film (for example, an i-type semiconductor Ji) 17b', and a first conductivity type (for example, an n-type) semiconductor ii 17c' are sequentially stacked.

It goes without saying that the number of photoelectric conversion layers 17' is not limited to three, and it is sufficient to laminate two or more of them.
A part of the insulating layer 11 is removed by etching to form a source electrode 13'.
and the lower electrode 19, and the transparent electrode 18' is connected to the gate electrode 15' (not shown).

As shown above, the second layer consists of multiple photoelectric conversion layers laminated.
It is preferable that the photoelectric conversion element (or the potash, which can also be said for the first photoelectric conversion element), has the structure described in Japanese Patent Application No. 1-44123, which the applicant previously filed.Specifically, L≦ A plurality of photoelectric conversion layers each having a semiconductor thin film that photoelectrically converts light with a wavelength of 1/α(λ) are stacked together [where λ is the wavelength of input light, α(λ) is the semiconductor thin film for photoelectrically converting light with a wavelength of λ] absorption coefficient, L; carrier collection length] is a photoelectric conversion element.In this case, the total thickness of the semiconductor thin film that performs photoelectric conversion of the stacked photoelectric conversion layers; d; the number of stacked photoelectric conversion layers; n; When L<d<nL
It is preferable that the number of photoelectric conversion elements be 1/[α(λ)·L] or more.Next, the operation of the semiconductor device of the present invention will be described. Note that C in FIG. 4 is the stray capacitance on the load side.

When light input enters, the first photoelectric conversion element 1 in the array configuration
generates a positive voltage as a control output, and the second photoelectric conversion element 3 in the array configuration generates a negative voltage. In other words, the photoelectric conversion elements 1 and 3 are elements that generate electromotive force (voltage) upon receiving light.

Due to the positive voltage generated by the first photoelectric conversion element 1, a current flows in the direction shown by the two-dot chain line in FIG. 4, and the capacitor C is charged. On the other hand, since the negative voltage generated by the second photoelectric conversion element 3 is applied between the gate G and the source S, the insulated gate field effect transistor 2 is in a reverse bias state and remains cut off. Then, while there is optical input, the second photoelectric conversion element 3
The negative voltage generated remains applied between the gate G and source S.

When the light input disappears, the first photoelectric conversion element 1 and the second photoelectric conversion element 3 stop generating voltage. Then, a positive voltage due to the accumulated charge in the capacitor C is applied between the gate G and the source S via the resistance element 4 (the second photoelectric conversion element 3 exhibits high resistance to positive voltage), resulting in a forward bias state. As a result, the insulated gate field effect transistor 2 becomes conductive, and a discharge current flows in the direction shown by the dashed line in FIG. 4, causing the charge in the capacitor C to disappear.

Note that the insulated gate field effect transistor 2 is usually
N-channel type is often used. In the case of an N-channel type insulated gate field effect transistor, the second photoelectric conversion element 3 applies a negative voltage between the gate G and the source S. In this case, the applicable range is wide.

Examples of the load controlled by the output of the semiconductor device according to the present invention include, but are not limited to, power field effect transistors. When the load is a power field effect transistor, the gate capacitance of this transistor corresponds to the floating capacitor C.

[For production]

In the semiconductor device of the present invention, when there is optical input, the second photoelectric conversion element continues to apply a negative (positive) voltage between the gate and source, so the threshold voltage shifts to a negative (positive) voltage. Then, when light is extinguished, the accumulated charge on the load side applies a positive (negative) voltage between the gate and the source, so that the threshold voltage that has shifted to negative (positive) is returned to its original value. therefore,
Since the threshold voltage does not fluctuate greatly and is maintained within a range close to the initial value, normal function can be achieved over a long period of time.

Since the second photoelectric conversion element has multiple photoelectric conversion layers, a sufficient voltage can be applied between the gate and source when there is optical input, and even if there are multiple photoelectric conversion layers, , are all provided on the insulated gate field effect transistor, so the chip area does not increase and the device does not become larger.

〔Example〕

Next, one embodiment of the semiconductor device according to the present invention will be described with reference to the accompanying drawings. This invention is not limited to the following embodiments.

FIG. 3 shows an embodiment of the semiconductor device of the present invention.

This semiconductor device has a configuration similar to the electric circuit shown in FIG. ing. Since the insulated gate field effect transistor 2 and the second photoelectric conversion element 3 have the same configuration as in FIG. 1, detailed description thereof will be omitted.

The first photoelectric conversion element 1 and the resistance element 4 are provided on an insulating substrate 10 with an insulating layer 21 in between.

The first photoelectric conversion element 1 has a structure in which three photoelectric conversion elements ff123 are stacked between a lower electrode 22 of Cr or the like and a transparent electrode (for example, an ln!Os layer) 24. Each photoelectric conversion layer 23 is made of, for example, amorphous silicon, and includes a first conductivity type (for example, n-type) semiconductor layer 23a and a low impurity concentration layer (for example, an i-type semiconductor layer) that is a photoelectric conversion thin film layer.
23b and a second conductivity type (for example, p-type) semiconductor layer 23c are sequentially stacked. The number of photoelectric conversion layers 23 is not limited to three, and a required number may be stacked.

The resistance element 4 has a structure in which conductive electrodes 42 and 43 are provided on both sides of a stacked body made up of three semiconductor layers 4I. Each semiconductor layer 41 is made of, for example, amorphous silicon, and is made of a first conductivity type (for example, n-type) semiconductor layer 41.
a, low impurity concentration layer (for example, i-type semiconductor layer) 41b, which is a photoelectric conversion thin film layer, second conductivity type (for example, p-type) semiconductor 1
This is a structure in which i41c is sequentially laminated. Each semiconductor layer 4
1 and each photoelectric conversion Jii 23 have the same layer structure and were formed at the same time. Furthermore, since the photoelectric conversion layer N17 and the photoelectric conversion layer 23 have the same layer structure, they can be formed at the same time.

Note that, as shown in FIG. 3, the transparent electrode 18 is connected to the lower electrode 22.
In addition, the transparent electrode 24 is formed to be connected to the conductive electrode 42. Further, unless shown in the drawings, the conductive electrode 43 is connected to the gate electrode 15 of the insulated gate field effect transistor 2, and the conductive electrode 42 is connected to the gate electrode 15 of the insulated gate field effect transistor 2.
is connected to the drain electrode 13 of.

〔Effect of the invention〕

As described above, in the semiconductor device according to claims 1 to 4, the change in the threshold voltage of the insulated gate field effect transistor is suppressed by the second photoelectric conversion element, so that the semiconductor device can maintain normal function for a long period of time. You will be able to perform to your full potential, and
Since the second photoelectric conversion element is provided on the insulated gate field effect transistor and the device does not become large in size, it is also excellent in practicality.

Further, the semiconductor device according to the third aspect is easy to manufacture, and the semiconductor device according to the fourth aspect has good performance as an insulated gate field effect transistor.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view of a main part of one embodiment of a semiconductor device according to the present invention, and FIG. 2 is a cross-sectional view of a main part of another embodiment of a semiconductor device according to the present invention. 3 is a cross-sectional view of an entire embodiment of a semiconductor device according to the present invention, FIG. 4 is an electric circuit diagram showing an equivalent circuit of the semiconductor device according to the present invention, and FIG. 5 is an insulated gate diagram. Figure 6 is a graph showing the relationship between the voltage applied to the gate electrode of an insulated gate field effect transistor and the change in threshold voltage, and Figure 7 is a cross-sectional view of a conventional semiconductor device. It is an electric circuit diagram showing the equivalent circuit of . 1... First photoelectric conversion element 2... Insulated gate field effect transistor 3... Second photoelectric conversion element 4... Resistance element 15.15'... Gate electrode 16.16'. ...Insulating layer 17.17'...
・Photoelectric conversion layer

Claims (1)

[Claims] 1. A first photoelectric conversion element that generates an output in response to optical input, and an insulated gate field effect transistor connected in parallel to the first photoelectric conversion element; A second photoelectric conversion element that generates an output for cutting off the insulated gate field effect transistor in response to the optical input, in a semiconductor device configured to cut off during the output of the photoelectric conversion element and turn on when the output disappears. Equipped with
A semiconductor device characterized in that the second photoelectric conversion element is comprised of a plurality of photoelectric conversion layers and is provided on the insulated gate field effect transistor. 2. A second photoelectric conversion element and a resistance element connected in series to the same element are connected in parallel to an insulated gate field effect transistor, and the intermediate point between the second photoelectric conversion element and the resistance element is connected to the insulated gate. 2. The semiconductor device according to claim 1, wherein the semiconductor device is connected to a gate electrode of a type field effect transistor. 3. The semiconductor device according to claim 1, wherein the gate electrode of the insulated gate field effect transistor is provided on an insulating layer laminated on the semiconductor layer. 4. The semiconductor device according to claim 1, wherein the gate electrode of the insulated gate field effect transistor is provided in advance below an insulating layer on which a semiconductor layer is laminated.