JPH0324656A - data storage device - Google Patents

Abstract

PURPOSE:To easily analyze the transmission/reception of past data when a fault occurs in a system by making it possible to store the large volume of data between a host computer and a peripheral device. CONSTITUTION:An address signal applied to plural peripheral devices 3 and a previously specified address signal out of signals on an interface cable 10 connecting the host computer 1 and respective peripheral devices 3 are checked by a circuit 5. When these address signals coincide with each other, data are stored. Two non-volantile external storage devices 7 such as floppy disk devices are provided so that the volume of data to be stored is not restricted and the stored data are not lost even when a power supply to the device is disconnected and respective storage devices are alternately used.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to data exchange between a host computer and one or more peripheral devices connected to the host computer at an interface between the host computer and one or more peripheral devices connected to the host computer. The present invention relates to a data storage device that stores data, and particularly relates to a data storage device that stores data transmitted and received between a specific peripheral device and a host computer.

[Prior Art] Generally, an interface for connecting a host computer and one or more peripheral devices includes a data interface cable (BUS) and a control interface cable (TAG). In such an interface, conventional technology for storing data sent and received between a host computer and a peripheral device is such that all signals on the aforementioned interface cable can be stored in memory for a certain period of time. It is configured.

In addition, as a conventional technology regarding this type of data storage device,
For example, a technique described in Japanese Patent Laid-Open No. 59-20026 is known. [Problems to be Solved by the Invention] The above-mentioned conventional technology transmits all interface signals between the host computer and all peripheral devices connected to one channel device of the host computer in the order in which the interface signals are generated. Since it is stored in memory,
The problem is that once all the memory is used, no more signals can be stored. Furthermore, the conventional technology cannot accumulate signals focused on one peripheral device or accumulate a large amount of signals, and the data once accumulated is lost when the device's power is cut off. There are problems. Furthermore, when attempting to analyze data for only one peripheral device, it is necessary to discard data for other peripheral devices and collect and analyze data for only one peripheral device. In such cases, it takes time to analyze the data, and there is a limit to the amount of data stored, so there may be a lack of data regarding the peripheral device and it may not be possible to analyze the data. It has some problems.

SUMMARY OF THE INVENTION An object of the present invention is to solve the problems of the prior art, and to store only data sent and received between a host computer and one peripheral device in an external storage device such as a disk device, which is a non-volatile data storage means. An object of the present invention is to provide a data storage device that can store a large amount of data.

[Means for Solving the Problems] According to the present invention, the above object is to provide signals to each peripheral device among signals on an interface cable connecting a host computer and a plurality of peripheral devices. By providing a circuit that checks the address signal and a pre-specified address signal, and storing data when these address signals match, it also limits the amount of data that can be stored. In order to prevent data loss and to prevent stored data from being lost even if the power to the device is cut off, two non-volatile external storage devices such as floppy disk drives are installed, and two external storage devices are installed. This can be achieved by using the two alternately.

[Function] If the address of one peripheral device from which data is to be collected is set in advance, the check circuit can select the data from among the data transmitted and received between the host computer and a plurality of peripheral devices. It is possible to identify the data transmitted and received between the host computer and one peripheral device whose information is to be collected, and control the storage of only that data in the external storage device. As a result, the data stored in the external storage device is only the data transmitted and received between one peripheral device and the host computer.

In addition, it is equipped with two external storage devices such as floppy disk drives, so if one disk becomes full, it can automatically switch to the other device and continue storing data. There is no limit to the amount of storage.

[Embodiment] Hereinafter, an embodiment of the data storage device according to the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing the system configuration of an embodiment of the present invention, FIG. 2 is a block diagram showing the configuration of an input/output adapter, FIG. 3 is a flowchart explaining the operation of the embodiment of the present invention, and FIG. FIG. 4 is a diagram illustrating the format of a temporary storage memory for interface data. Figures 1 and 2
In the figure, l is the host computer, 2 is the channel,
3 and 9 are peripheral devices, 4 is a data storage device, 5 is an input/output adapter, 6 is a controller, 7 is a storage device, 8 is a termination device, 10 is an interface cable, 202 is a pulse converter, 204 is an address hold flip-flop Frotub,
209 is an address matching flip-flop, and 211 is a command hold flip-flop.

As shown in FIG. 1, a system including a data storage device according to an embodiment of the present invention includes a host computer 1 having a channel device 2, a plurality of peripheral devices 3, and a data storage device 4 according to the present invention. They are connected via an interface cable 10. The interface cable 10 connects the data storage device 4 and a plurality of peripheral devices 3 in a chain-like fashion, and is terminated by a termination device 8 at the last peripheral device. Therefore, the data storage device 4
is connected in the same way as a plurality of peripheral devices, and from the perspective of the channel device 2, it is just one peripheral device.

The signals created by the host computer 1 or the signals created by the peripheral device 3 are transmitted to the channel device 2.
The information is transmitted and received between the host computer 1 and the peripheral device 3 via the interface cable 10 and the interface cable 10. Signals transmitted and received via this interface cable 10 are broadly classified into data-related signals and control-related signals, and are transmitted on cables generally called BUS lines and TAG lines, respectively. It should be noted that each signal system transmitted to this interface cable 10 is well known, so a description thereof will be omitted. In the system according to the embodiment of the present invention configured as described above, the data storage device 4 may be connected anywhere as long as it is connected closer to the channel device 2 than the peripheral device 3 from which data is to be collected. .

In the system of one embodiment of the present invention shown in FIG.
A configuration in which the peripheral device 9 is connected to the data storage device 4 is also shown, but in this configuration, it is equivalent to the data storage device 4 existing inside the peripheral device 9, and this peripheral device 9
However, data transmitted and received between other peripheral devices 3 and the host computer 1 will be stored in the data storage device 4 within the own device.

The data storage device 4 also includes an input/output adapter 5 that controls data input/output, a controller 6 that controls the BUS line and TAG line described above, and a storage device RA7 that stores data. It is configured.

FIG. 2 is a diagram showing a circuit in the input/output adapter 5 that synchronizes the data transfer rate on the interface cable 10 and the processing speed of the controller 6. This circuit is an address hold flip-flop that is set by an address capture request detection 203 that indicates that an address capture request has been made on the TAG line of the interface cable 10 and is reset by a report 201 that address capture is completed. whelk 2
04, and while the flip-flop 204 is set, interface processing for transmitting and receiving data between the channel device 2 and the peripheral device 3 is interrupted.

Hereinafter, the operation of analyzing the address signal of the peripheral device 3 in the controller 6 will be explained with reference to the flowchart shown in FIG. 3, and the operation of the circuit shown in FIG. 2 will be explained.

(1) First, the input/output adapter 5 monitors the signal on the TAG line by the address capture request detection circuit 203, and when an address capture request is detected, the pulse converter 202
The address hold flip-flop 204 is set via the address hold flip-flop 204. When this flip-flop 204 is set, an ADD-IN signal 205 is sent from the peripheral device 3 to the channel device 2 to indicate an address match to the logic gate 205.
or the address reception signal ADD-INH sent to the peripheral device 3 from the channel device Wl2.
be similarly suppressed. As a result, the data transmission/reception process between the host computer 1 and the peripheral device 3 via the interface cable IO cannot proceed to the next operation and is temporarily suspended. controller 6
During this time, in order to know the operation of the input/output adapter 5 mentioned above, the state of the address hold flip-flop 204 is monitored (steps 301 and 302).

(2) In step 302, when the set state of the address hold flip-flop 204 is detected, the address information on the BUS line is fetched, and whether the address matches the preset trace designation address or not. Check whether or not. If this check does not match, after issuing the address import completion report 201 (step 30
9) Repeat the process from step 301. The above-mentioned trace designation address is the address of the peripheral device 3 that sends and receives data to be captured to and from the host computer 1.
This was instructed in advance. The method of setting this address does not need to be limited to the method described above, and any known method may be used (steps 303, 304). (
3) If it is determined in step 304 that the address on the BUS line matches the preset trace designation address, the controller 6
The address matching report 208 is issued to the address matching report 208, and the temporary storage memory is initialized (steps 305, 306).

This address match report 208 is, for example, an inverter,
Pulse converter 202 consisting of a delay circuit and a NAND circuit
is applied to the set terminal of the address match flip-flop 209 through the address matching flip-flop 209 to set the flip-flop 209. This flip-flop 209 is then used to determine whether or not to import command data, text data, etc. sent over the interface cable 10 into a memory that temporarily stores them, and to terminate the command, that is, to It is reset at the end of data transfer.

(4) When the initialization of the temporary storage memory in step 306 is completed, a pulse is output to CNTRL BITO and an address capture completion report 201 is issued. This address capture completion report 201 is applied to the reset terminal R of the flip-flop 204 via the pulse converter 202 to reset the flip-flop 204, as in the case of the address match report described above. As a result, AD, which was suppressed during the initial processing of the temporary storage memory mentioned above,
The D-IN signal 206 is sent to the peripheral device 3 as an ADD-IN signal 207, or the ADD-INH signal is sent to the channel device 2 (step 307).

Through the above-described operation, the data storage device 4 according to the present invention captures only the data transmitted and received between the peripheral device 3 having a specific address and the host computer l, and
Preparations for storage have been made, and data transmission/reception processing between the host computer 1 and the peripheral device 3 will proceed next.

The sequence of data transmission and reception processing between the host computer l and the peripheral device 3 is performed in the same manner as commonly known as an I/O interface, and command data is then transferred onto the interface cable 10. That will happen.

(5) Therefore, the data storage device 4, which has detected the address match, then reads the signal on the TAG line again and monitors whether a command capture request is transmitted and received between the channel 2 and the peripheral device 3. , when the request is detected, sets the command hold flip-flop 211 and performs processing to take in the command information on the BUS line. The process of capturing this command information is executed using the same logic as the process of capturing address information described above, and the command information is stored in the temporary storage memory (step 308).

Furthermore, text data will continue to be transferred onto the interface cable 10, and the process of importing this text data will also be performed using the same logic as described above, and the text data will be stored in a temporary storage memory. The temporary storage memory is configured with the format shown in Figure 4. In other words, the temporary storage memory is
It consists of one 256-byte block having a command section, status section, data counter section, and data section, and n 256-byte blocks containing only the data section. The memory capacity of this temporary storage memory may be arbitrarily determined depending on the storage device [7] to be used. In one embodiment of the present invention, a 256-byte/sector, 8-sector/track floppy disk was used as the storage device 7, and the maximum capacity of the temporary storage memory was 50 Kbytes. The data stored in the temporary storage memory 401 is written to the floppy disk after the data has been stored in all the data blocks. This may be done at the timing after writing the status indicating the status of the peripheral device 3 to be reported to the host computer in the second byte of the status field. Two storage devices 7 configured as floppy disk devices are provided so as to be switchable, and when the floppy disk of one device becomes full due to the write process described above, the storage device 7 is switched to the other device. Once this change has been made, this state can be indicated by a well-known method, such as a lamp, and the floppy disk can be replaced with a new one.

According to one embodiment of the present invention described above, only the data transmitted and received between a specific peripheral device and the host computer can be extracted and accumulated in extremely large quantities, and data can be analyzed with a sufficient amount of data. etc. can be done. The embodiment of the present invention described above focused on a specific peripheral device and accumulated data sent and received between that peripheral device and the host computer, but the present invention It can be modified to store data sent and received from the host computer in a manner compatible with peripheral devices. In this case, the data storage device according to the present invention takes in all the data on the interface cable, and stores the data being sent and received between the peripheral device and the host computer for each address of the peripheral device to the corresponding external storage device. All you have to do is record it in the area where you want it to be.

Further, in the present invention, an output device such as a printer can be used instead of the external storage device in the above-described embodiment.

[Effects of the Invention] As explained above, according to the present invention, it is possible to focus on a specific peripheral device and accumulate a large amount of information on data transmission and reception between that peripheral device and a host computer over a long period of time. This makes it easy to analyze what data was sent and received in the past in the event of a system or peripheral device failure. In addition, if the peripheral device is an output device such as a printer, and that output device becomes a failure, the accumulated data can be given to another output device to output it, and the processing results of the two output devices can differ. By checking this, you can test the status of the output device that caused the problem.

[Brief Description of the Drawings] Figure 1 is a block diagram showing the system configuration of an embodiment of the present invention, Figure 2 is a block diagram showing the configuration of an input/output adapter, and Figure 3 is a block diagram showing the configuration of an input/output adapter. FIG. 4 is a flowchart explaining the operation and a diagram explaining the format of the temporary storage memory for interface data. ! ...Host computer, 2...Channel, 3, 9...Peripheral device, 4...
Data storage device, 5... Input/output adapter, 6.
...Controller, 7...Storage device, 8
... Termination device, lO ... Interface cable, 202 ... Pulse converter, 20
4...Address hold flip-flop, 2
09...Address matching flip-flop, 21
1l Figure l Figure 2

Claims (1)

[Claims] 1. In a system in which a host computer and one or more peripheral devices are connected by an interface cable, a specific peripheral device is specified and a connection between the specific peripheral device and the host computer is provided. A data storage device that captures and records transmitted and received data when the data is on the interface cable. 2. Data characterized in that in a system in which a host computer and one or more peripheral devices are connected by an interface cable, all data transmitted and received on the interface cable is captured and recorded in correspondence with the peripheral devices. Accumulator. 3. The data storage device according to claim 1 or 2, wherein the data capture and recording is performed by at least two switchable nonvolatile data recording means. 4. A peripheral device characterized by having therein the data storage device according to claim 1, 2, or 3. 5. In a system in which a host computer and one or more peripheral devices are connected by an interface cable, a specific peripheral device is specified, and the data sent and received between that specific peripheral device and the host computer is A peripheral device that captures and prints out data when it is on an interface cable.