JPH0324735A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To realize microstructure of each transistor by forming junction isolating layers on both ends of an Si active region, depositing wiring material without forming an interlayer insulating film, and forming a wiring layer of self alignment type contact by patterning. CONSTITUTION:After a polysilicon gate 6 is formed, a spacer of an oxide film 12 is formed on the side wall of a gate electrode 6, and a single crystal silicon layer 11 of an SOI substrate is etched by using the oxide film 12 as a mask. By oblique ion-implantation method for this part, or thermal diffusion after a silicon based spreading film containing impurity is spread, junction isolating layers 11, 13 of the Si active region are formed; wiring material 10 is deposited without depositing an insulating film, and a self alignment type contact is formed by patterning. Thereby contact forming process can be simplified, and the area of a contact region can be reduced, so that the microstructure of isolation of the Si active region is realized.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method for manufacturing a semiconductor device.
This invention relates to a method for separating a Si active region in an I (Silicon on Insulator) structure.

[Conventional technology]

FIG. 3 shows a conventional method for separating a Si active region in a Sol structure.

A high dose of oxygen ions is applied to the semiconductor substrate 1 at a rate of 1'50 to 20%.
A buried insulating layer 2 of a silicon oxide film is formed under a thin (1000 to 2000 thick) layer 3 of crystalline St by deep implantation with an acceleration energy of 0 KeV, and then field oxidation is performed to form an element isolation region 4. After that, a gate oxide film 5 is formed, a gate electrode material 6 and an oxide film 7 are deposited, and a patterning resist mask 8 is used to form the electrode material 6.
Then, the oxide film 7 is patterned to form a gate electrode.

Next, low concentration ions are implanted into the source/drain regions as shown in FIGS. 3-), oxide film spacers 12 are formed on the side walls of the gate electrode, and these are used as masks as shown in FIGS.
Perform high concentration ion implantation as shown in C).
D (Lightly Doped Drain) is formed, then an interlayer insulating film 9 such as a silicon oxide film is deposited as shown in FIG. to form a transistor.

This Sol structure does not require a deep diffusion layer, suppresses the latch-up phenomenon of parasitic transistors, and reduces the area of the p-n junction region, significantly reducing capacitance.
The switching speed of each transistor is increased, short channel effects associated with high integration can be minimized, and miniaturization is possible. Furthermore, since the St active region can be made small, it has the advantage that it is possible to reduce soft errors caused by photocurrents and α particles caused by impact ionization.

[Problem to be solved by the invention]

Since the conventional SOI structure semiconductor device is constructed as described above, it is necessary to form an element isolation region using field oxidation as a method for isolating the Si active region of the transistor, and furthermore, it is necessary to form an element isolation region using field oxidation as a method for isolating the Si active region of the transistor. When connecting to the drain region, it was necessary to ensure a sufficiently wide area between the gate electrode and the contact to prevent it from electrically shorting with the gate electrode. Therefore, with miniaturization,
Despite the shortening of the gate length, there was a problem in that the isolation method was not sufficiently miniaturized.

This invention was made in order to solve the above-mentioned problems, and it is possible to miniaturize the isolation region of the Si active region of a transistor in an SOI structure and form a self-aligned contact, and to create a semiconductor device that can be miniaturized. The purpose is to obtain a manufacturing method.

[Means to solve the problem]

In the method for manufacturing a semiconductor device according to the present invention, as a method for separating the Si active region of a transistor, after forming a polysilicon gate, an oxide film spacer is formed on the side wall of the gate electrode, and this oxide film is used as a mask to form an SOI substrate. The single-crystal silicon layer is etched and a silicon-based coating film (SOG) containing impurities is applied to this part by oblique ion implantation or by etching the single crystal silicon layer.
A junction isolation layer for the Si active region is formed by applying and thermal diffusion, and a self-aligned contact is formed by depositing and patterning a wiring material without depositing an insulating film. This is what I did.

[Effect]

In this invention, since the method having the above structure is used, the contact formation process can be simplified, the area of the contact region can be reduced, and the separation of the St active region can be miniaturized.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

In FIG. 1, l is a semiconductor substrate, 2 is an oxide film, 3 is a crystalline silicon layer (Sol), 5 is a gate insulating film such as an oxide film, 6 is a gate electrode, 7 is an oxide film, and 8 is a gate patterning. 10 is a wiring layer, 11 is a low concentration impurity layer, 12 is an oxide film spacer, and 13 is a high concentration impurity layer.

FIG. 2 shows a top view of FIG. 1(a), and l4 is an element isolation region.

Next, Figure 1. The manufacturing method of the present invention will be explained according to Figure 2. As shown in FIG. 1(a), the present invention is based on a Sol structure in which an oxide film 2 is formed on a semiconductor substrate 1, and a thin crystalline silicon layer 3 is formed on the oxide film 2. When forming an n-channel transistor, this crystalline silicon layer 3 is made into a p-channel layer by implanting, for example, B ions at a dose of 2×10''/c1 and an implantation energy of 30 Ke. In this structure, CMOS} When forming a transistor, as shown in Figure 2, it is necessary to separate both sides of the channel, so the source and
Both sides perpendicular to the drain direction are normal LOCOS
An element isolation region 14 is formed by field oxidation using a method or the like, and the source and drain directions of adjacent transistors are connected by crystalline silicon 3 having a Sol structure.

Next, as shown in FIG. 1(a), after forming a gate oxide film 5, a gate electrode material 6 and an oxide film 7 are deposited, and a resist mask 8 for patterning is used to form a gate electrode 6. .

Next, when forming an n-channel transistor, a low concentration of impurity is applied to the entire surface of the wafer so that n-channel transistors are formed. For example, As is ion-implanted at a dose of IXIO''/C-1 and an implantation energy of 30 KeV to form the low concentration impurity layer 11.

Next, as shown in FIG. 1(b), an oxide film is deposited and anisotropically etched to form oxide film spacers 12 on the side walls of the gate electrode 6.

Next, as shown in FIG. 1(C), using the spacer l2 of the oxide film as a mask, a low concentration impurity Fi of crystalline silicon is injected.
ll is anisotropically etched and separated.

Next, low-concentration impurities were added using oblique ion implantation. For example, A
s dose: IXIO”/C, implantation energy: 30
Ion implantation is performed using KeV to form a high concentration impurity layer n' layer 13 to form an LDD structure. As a result, a low concentration impurity layer 11 and a high concentration impurity layer N n ” are formed at both ends of the Si active region.
A junction separation layer consisting of layer 13 can be formed.

Alternatively, the form of this high concentration impurity layer n''7113 or a silicon-based inorganic coating film (SOC) containing diffusion impurities
The low concentration impurity W11 may be formed at both ends of the St active region in this way.
1 and a high concentration impurity N n ''1i13 is formed.

Next, as shown in FIG. 1(d), wiring material is deposited,
By patterning, the wiring layer 10 can be formed and self-aligned contacts can be formed.

As described above, in this example, as a method for separating the active region of a single crystal silicon layer, a junction separation layer is formed at both ends of the Si active region, and a wiring material is deposited and patterned without forming an insulating film between the eyebrows. Since a wiring layer is formed by self-aligned contacts by etching, each transistor can be miniaturized and high integration can be achieved.

〔Effect of the invention〕

As described above, according to the present invention, as a method for separating the active region of each transistor, after forming a polysilicon gate, an oxide film spacer is formed on the side wall of the gate electrode,
Using this oxide film as a mask, the single crystal silicon layer of the SOI substrate is etched, and after applying an oblique ion implantation method or a silicon coating film (SOG) containing impurities to this part, a crystalline silicon layer (Sol) is formed. 4 is element II
iii region, 5 is a gate insulating film, 6 is a gate electrode, 7 is an oxide film, 8 is a resist mask for patterning, 9 is an insulating film between the eyebrows, 10 is a wiring layer, 11 is a low concentration impurity layer, 12
13 is an oxide film spacer, 13 is a high concentration ion implantation layer, and 14 is an oxide film spacer.
is an element isolation region.

Note that the same reference numerals in the figures indicate the same or equivalent parts.

By depositing and patterning the wiring material without depositing an edge film, the wiring layer is formed with self-aligned contacts, which enables miniaturization of the isolation method for each active region, and enables higher integration. There are effects that can be achieved.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional side view showing a process flow of a method for manufacturing a semiconductor device according to an embodiment of the present invention, FIG. 2 is a top view of FIG. 1(a), and FIG. 3 is a process flow of a conventional method. It is a collapse side view.

Claims (1)

[Claims] (1) In a method for manufacturing a semiconductor device with an SOI structure, in which an insulating film layer is formed on a semiconductor substrate, and a thin single crystal silicon layer is formed on the insulating layer, a polysilicon gate electrode is formed on the single crystal silicon layer. forming an oxide film spacer on the side wall of the electrode, etching the single crystal silicon layer using the oxide film spacer as a mask, and etching the single crystal silicon layer diagonally using the oxide film spacer and the oxide film on the polysilicon gate electrode as a mask. Perform impurity implantation or apply a silicon-based inorganic coating film containing diffusion impurities,
By performing thermal diffusion, a junction isolation layer is formed at both ends of the Si active region, and by depositing and patterning a wiring material without depositing an interlayer insulating film, a wiring layer with self-aligned contacts is formed. A method for manufacturing a semiconductor device, characterized in that: