JPH03249698A - Image processing device - Google Patents

Abstract

PURPOSE:To freely alter an area which is supplied as a visible image to a monitor by providing a supply means which supplies an image signal in a specific area in an object image to a monitor so that the signal is regenerated as the visible image and a means which controls the supply means so that the specific area is altered corresponding to the time. CONSTITUTION:An input analog video signal such as a playback video signal is digitized by an A/D converter 40. A synchronizing separation circuit 45 separates signals corresponding to a vertical synchronizing signal(VD) and a horizontal synchronizing signal(HD) from the digital video signal outputted from the A/D converter 40 and supplies them to a timing controller 46. The timing controller 46 determines the output timing of each control signal in synchronism with the supplied synchronous signals VD and HD. Then a control means alters the specific area in order with time and the supply means is so controlled that the area is supplied as the visible image to the monitor. Consequently, the specific area in the object image is altered sequentially, so various processes are performed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an image processing device, and particularly to an image processing device having a function of enlarging an image.

[Conventional technology]

Conventionally, when forming a video signal by enlarging a part of the image represented by the video signal, the original video signal is first stored in a random access memory (RAM), and the read address of the RAM is controlled according to a predetermined program. A common method was to achieve this by doing so.

Hereinafter, such a conventional method will be briefly explained.

Now, a case will be described in which a video signal showing an enlarged image as shown in FIG. 9(B) is formed from a video signal showing an original image as shown in FIG. 9(A).

FIG. 2 is a diagram showing an example of the configuration of a conventional enlargement processing circuit, and FIGS. 3(A) and 3(B) are diagrams for explaining the operation of the circuit in FIG. 2.

In FIG. 2, an analog video signal representing an original image inputted from an input terminal 20 is converted into a digital signal by an A/D converter 21, and is converted into a digital signal by a field memory 2 consisting of a RAM.
2.

As shown in FIG. 3(A), the storage areas in the field memory 22 correspond to each pixel of the input digital image signal, and the supplied digital video signal corresponds to each pixel in the field memory 22. It is stored in correspondence with the specified write address. When reading the digital video signal stored in the field memory 22 as described above, for example, as shown in FIG. 3(B), the digital video signal corresponding to the pixel corresponding to the center of the screen is Address (3-3゜3-4.4-3. in the figure)
4-4) The digital video signal stored in
-3", "3-3", "3-4", 3-4", etc. The image is enlarged twice by repeating reading twice in the horizontal scanning direction and twice in the vertical scanning direction. It forms a digital video signal corresponding to Incidentally, such address control is performed by synchronizing the A/D converter 21 and the D/A converter 23 with the address control circuit 24 which operates according to the timing signal output from the timing control signal generation circuit 25 shown in FIG. It is being carried out while taking. In FIG. 2, W indicates a write address control signal that controls writing to the field memory 22, and R indicates a read address control signal that controls reading from the field memory 22. As described above, the digital video signal read from the field memory 22 is converted into an analog signal by the D/A converter 23, and the D/A converter 23 outputs an analog video signal corresponding to the desired enlarged image. Ru.

The present applicant has also previously filed an application for a method of realizing the above-mentioned enlargement process using a so-called first-in-first-out memory (hereinafter referred to as FIFO).

[Problem to be solved by the invention]

In view of this, an object of the present invention is to provide an image processing device that can freely change the area that is supplied as a visible image to a monitor.

[Means to solve the problem]

In order to achieve the above-mentioned object, the present invention provides a supply means for supplying an image signal of a predetermined area in a target image to a monitor in order to reproduce it as a visible image, and a supply means for supplying an image signal of a predetermined area in a target image to a monitor so as to sequentially change the predetermined area according to time. and means for controlling the means.

[Effect]

In the above configuration, the supply means is controlled by the control means so that the predetermined area is sequentially changed according to time and is supplied as a visible image to a monitor.

〔Example〕

An embodiment of the present invention will be described below.

FIG. 4 is a block diagram showing the configuration of a video signal processing circuit as an embodiment of the present invention, and an analog video signal such as a reproduced video signal output from a VTR is supplied to an input terminal indicated by IN in the figure. has been done. This input analog video signal is digitized by an A/D converter 40.

In FIG. 4, after the A/D converter 40, the D/D converter 40, which will be described later,
It is assumed that all components up to A converter 50 handle digital video signals.

In the processing circuit shown in FIG. 4, when enlargement processing is not performed, a selection signal generator 49 operating according to control data from a system controller 47 generates an output control signal S.
P is output, and the switch 44 is connected to the A side in the figure by the output control signal SP. This operation causes input terminal I
The same analog video signal as the analog video signal input from N is output from the output terminal OUT.

Next, image enlargement processing according to the present invention will be explained.

Figures 5 and 6 show F in Figure 4 when the image is enlarged.
These are timing charts for explaining the processing timing of the IFO 41. FIG. 5 shows the processing timing during vertical scanning, and FIG. 6 shows the processing timing during horizontal scanning. FIG. 7 is a schematic diagram used to explain image enlargement processing.

The synchronization separation circuit 45 separates signals corresponding to a vertical synchronization signal (VD) and a horizontal synchronization signal (HD) from the digital video signal output from the A/D converter 40, and supplies the signals to the timing controller 46.
6, the output timing of each control signal is determined in synchronization with the supplied synchronization signals VD and HD.

In FIG. 5, VD is a vertical synchronization signal, and WE is F
A write enable signal for the IFO 41, RE a read enable signal, WR a write reset signal, RR a read reset signal, WD write image data, and RD read image data.

Now, a case will be described in which a video signal corresponding to an enlarged image of the area a on the screen shown in FIG. 7 is formed. As shown in FIG. 5, the write enable signal WE indicates that the image data corresponding to the area a and area s in FIG.
During the period when it is supplied to the FO41, it is at a high level (H) that allows writing, and during the other periods it is at a low level (L) that disables writing.
Only the image data corresponding to the area S is written. To explain in more detail, this write enable signal WE indicates that the image data corresponding to the point R in FIG.
It changes to H at the timing when it is supplied to IFO 41, and changes to L after each field period. The timing at which this write enable signal WE changes to H is the timing shown by R in FIGS. 5 and 6. On the other hand, the write reset signal WR is a pulse signal that is generated once every two fields in synchronization with the vertical synchronization signal in the case shown in FIG. 5 during the period when the write enable signal is L, and F
The frequency of the write clock wc to IFO41 is 1 field memory during 1 field period.
This is the frequency at which image data can be written in all areas of 41. Therefore, assuming that the FIF041 has a storage capacity to store image data corresponding to one field's worth of video signals, the image data corresponding to the area a and area A in FIG. data corresponding to the number of fields will be written to the FIFO 41 during the two-field period. The numerical values in the schematic diagram of the written image data WD in FIG. 5 are field numbers, and the shaded areas are F I F
This indicates a period in which there is no image data written to O41. Further, a, b, and C in the schematic diagram of written image data WD in FIG. 6 indicate image data corresponding to areas a, b, and c in FIG. 5, respectively.

On the other hand, the read clock RC is set to a frequency that is % of the write clock WC, and the image data for two fields is time-axis expanded by twice during the two-field period.
It will be read from FO41. Since the frequency of the read clock RC is outside the frequency of the write clock WC, the read enable signal RE must be H for twice the period of the write enable signal WE, and all periods except the vertical synchronization period are It becomes H in the period.

The read reset signal RR is a pulse signal that is generated once every two field periods in synchronization with the vertical synchronizing signal at the timing when image data corresponding to the upper left end in FIG. 7 is supplied to the FIFO 41, As a result, Fig. 5 RD,
Read data RD as schematically shown in FIG. 6 RD is obtained. That is, the read image data from FIF041 is
Each scanning line in the upper left corner of FIG. The structure is as follows.

CP in FIG. 5 indicates a control pulse supplied from the timing controller 46 to the switch 43,
As shown in the figure, during the horizontal scanning period when image data corresponding to area a is output from the FIFO 41, H
It becomes L during the horizontal scanning period when image data corresponding to one area is output. When the control pulse CP is L, the switch 43 switches the delay line (
IHDL) 424117, and when it is H, it is connected to the other side. Therefore, from this switch 43, the area a
Image data corresponding to is repeatedly output twice for each horizontal scan. Therefore, the image data outputted from this switch 43 becomes image data representing an image obtained by enlarging the image of area a in FIG. 7 twice. The 7th
5TART in the figure.

END will be described later in the explanation of FIG.

Next, FIG. 8(A) shows various output forms for displaying the enlarged image obtained as described above.

This will be explained using (B) and (C). First, when an output format for displaying only an enlarged image is instructed in the scanning section 48, the system controller 47 sends the selection signal generator 4
9 and connects the switch 44 to the B side in the figure in response to the selection control signal SP. In addition, the timing controller 4
6 is the write address reset of FIF041 in Figure 5.
By performing at the timing R shown in Fig. 6, the 8th
Image data corresponding to the image within the dotted line in the left diagram of FIG. The image data is supplied from the switch 44 connected to the B side in the figure to the D/A converter 50, converted into an analog video signal, and then output from the output terminal OUT.

Next, a case will be described in which a composite image of the enlarged image and the original input image is displayed. For example, when the operation unit 48 instructs an output format in which the right half of the screen of the display unit in the display device is displayed as an enlarged image and the left half as the original input image, as shown in FIG. 8(B), The system controller 47 controls the selection signal generator 49 and selects the selection control signal SP.
In the first half of each horizontal scanning period, the switch 44 is set to A in the figure.
side, the latter half is connected to side B in the figure. Further, the timing controller 46 resets the write address of the FIFO 41 at the timing when the image data corresponding to the portion indicated by R in the left diagram of FIG. 8(B) is supplied to the FIFO 41. The switch 43 outputs image data corresponding to an image obtained by connecting the images within the dotted line in the left diagram of FIG. Therefore, Fig. 5 (B
), the image data output from the switch 44 is such that the left half of the screen is the original input image, and the right half is an enlarged image that doubles the center of the left half image. The image data output from the switch 44 is supplied to the D/A converter 50, converted into an analog video signal, and then output from the output terminal OUT.

Further, when an output format is instructed in the operation unit 48 to display the left half of the screen of the display unit of the display device as an enlarged image and the right half as an original input image, as shown in FIG. 8(C),
The system controller 47 connects the switch 44 to the B side in the figure during the first half of each horizontal scanning period and to the A side in the figure during the second half using the selection control signal SP. Similarly, by timing the image data corresponding to the portion indicated by R in the left diagram of FIG. 8(C) to be supplied to the FIFO 41, the image data output from the switch 44 is Half is the original input image, and the left half is image data corresponding to an enlarged image obtained by enlarging the center part of the right half image twice, and the image data output from this switch 44 is sent to the D/A converter 50. supplied to,
After being converted into an analog video signal, it will be output from the output terminal OUT.

These image compositions can be similarly performed even if writing to the FIFO 41 is stopped and the enlarged image is made into a still image.

According to the video signal processing device of the embodiment as described above, enlarged images of various patterns and original images can be effectively synthesized with extremely simple operations, and furthermore, FIFO can be used in the circuit configuration. Because it has a simple circuit configuration, it is extremely effective in implementing such advanced processing into consumer equipment.

Note that the present invention is not limited to the specific circuit configuration shown in FIG.
The same can be achieved with a configuration using a random access memory as shown in the figure. In this case, the generation pattern of RAM write or read addresses should be stored in a look-up table such as a read-only memory (ROM), and the pattern generated from this ROM should be switched according to the selected composite pattern. A similar effect can be obtained. In addition, when using RAM in this way, even more complex composition patterns can be supported.According to Road, when compositing an enlarged image with another image, various composition patterns can be created with simple operations. be. 4 in Figure 1
Elements having the same functions as those in the figures are given the same reference numerals, and descriptions thereof will be omitted. 146.147.148 in Figure 1
are a timing roller, a system controller, and an operation section, respectively, and their operations are slightly different from those shown in FIG. In FIG. 1, the timing controller 146 is WC, W.
Pulses such as R, WE, RE, RR, and RC are outputted, and the main internal parts will be explained in particular.

a system clock from the system controller 147;
For example, the counter 202 counts f-c=3, 58 MHz and is cleared by the HD, and in the enabled state, if there is a clear command from the system controller 147, the counter 202 is cleared by the clear command.
A presettable up/down counter 201 and a counter 2 that count and continue to output data preset by a preset signal when not in an enabled state.
Comparison circuit 203 and comparator 203 that compare the outputs of 02
A counter 205 that counts the output of
The output of the HD is decoded, and the counted value of the HD is located at the vertical position on the screen shown in FIG.

a decoder 207 that generates a signal LL2 when a count value corresponding to , respectively, is reached; AND gates 209, 210 and an AND gate 210 for ANDing the outputs of the decoder 207, L, and the output of the comparator circuit 203; The flip-flop 212 is set by the output of the AND gate 209 and reset by the output of the AND gate 209.

Further, the operation section 148 has a switch 151 for giving a command to perform electronic panning. CA is a video camera having a lens L, and M is a monitor for reproducing the output of the D/A converter.

In this embodiment, while an electron beam, that is, a mode for enlarging a predetermined region in a given image signal, is being executed, an electron panning mode, that is, a mode for automatically shifting the predetermined region over time, is executed. be disclosed.

That is, as shown in FIG. 10, by shifting WE over time as shown by the dotted line, panning can be performed without moving the lens L of the video camera CA in FIG.
can be done.

Next, the above-mentioned operation will be explained using FIG. 10. When the switch 151 is turned on, the image in the area a in FIG. 7 is enlarged and supplied to the monitor M in the same way as described above in FIG.

In this state, the address of C1 shown in a of FIG. 7 is set in the presettable counter 201 by the system controller.

Therefore, in such a state, the comparator 203 generates an output in which the image address becomes H level in the area to the right of the line shown in FIG. 7 C1.

The counter 205 counts the number of horizontal lines of the input video signal based on the output of the comparator 203, and based on this count, the decoder 207 changes the number of lines to L, , L2, respectively, when the number of lines increases to , L, respectively. An H level signal is output to the indicated line. Therefore, since the AND gates 209 and 210 output H level signals at the timings shown at 5TART and END shown in FIG. 7, the flip-flop 212 outputs a signal multiplied by wE as shown by the solid line in FIG. Therefore, the FIFO memory 41 has a
, b are captured, and enlarged as described above in FIG. 4.

At this point, the operator presses the electronic panning switch 151.
When turned on, the system controller 147 controls the enable signal so that the up/down counter 201 performs a counting operation, and also issues a clear command to set the counter to a count-up state. Accordingly, the up/down counter 201 starts counting the input VD signals.

At the initial stage of counting, the up/down counter 201
The count value of is relatively small. Therefore, the comparator 203 generates a signal that becomes H level on the left side of the line C1 shown in FIG. As the VD signals are counted, the count value of the counter increases, and the CI line shown in FIG. 7 gradually moves to the right. The area a moves to the right on the screen over time. Such a state is shown by the dotted line WE in FIG.

On the other hand, in the image reproduced on the monitor M, the area shown in a of FIG. 7 is displayed in an enlarged manner. Therefore, by turning on the electronic panning switch 151 mentioned above, the enlarged image displayed on the monitor M is automatically panned even though the lens L of the video camera CA shown in FIG. 9 is not moved. .

In the above explanation, the case where the counting state of the counter 201 is set to the up state is described, but if a switch for setting the counting state of the counter 201 to the down state is provided in the operation unit 148, the direction of panning can be freely changed. Can be changed. Also, the system controller 14
Panning can be performed from any position on the screen by freely setting the value to be preset in the counter 201 from 7 to 7.

Also, if a variable frequency divider is provided at the input end of the counter 201, pa
The speed of nn i ng can be changed automatically.

Furthermore, in the above description, horizontal panning was performed, but by changing the settings of the decoder 207, vertical panning can be performed.

As explained above, according to this embodiment, electronic panning processing can be performed.

〔Effect of the invention〕

According to the present invention described above, since the predetermined area in the target image is sequentially changed over time, various processes such as panning processing can be performed.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of another embodiment of the present invention, FIG. 2 is a block diagram showing an example of the configuration of a processing circuit that performs conventional image enlargement processing, and FIGS. 3(A) and (B) are 3 is a schematic diagram for explaining the operation of the circuit shown in FIG. 2. FIG. FIG. 4 is a diagram showing the configuration of a video signal processing circuit as an embodiment of the present invention, and FIGS. 5 and 6 are diagrams for explaining the operation of each part of the circuit in FIG. 4 during image enlargement processing. Timing chart; Figure 7 is a schematic diagram for explaining image enlargement processing by the processing circuit in Figure 4; Figures 8 (A), (B), and (C) are enlarged images obtained by the circuit in Figure 4. 9(A) and 9(B) are diagrams showing an example of conventional image enlargement processing, and FIG. 10 explains the operation of the embodiment of FIG. 1. This is a timing chart. Field 5 Diagram (A1 tile exit 0D Mazu scale summary diagram ρ'

Claims (3)

[Claims] (1) A supply means for supplying an image signal of a predetermined area in a target image to a monitor for reproduction as a visible image, and a means for controlling the supply means so as to sequentially change the predetermined area according to time. An image processing device comprising: (2) The image processing device according to claim (1), wherein the predetermined area is a part of an area in the target image. (3) The image processing apparatus according to claim 1, wherein the supply means is a means for scaling the image signal of the predetermined area and supplying the same to a monitor.