JPH03250218A - Carry selective adding circuit - Google Patents

Abstract

PURPOSE:To reduce a circuit scale by replacing a full adder circuit to be used for a conventional carry selective adder circuit with an adder gate circuit. CONSTITUTION:As the first adder gate circuit composed of one two-input OR gate 1001 and one two-input EX-NOR gate 1002, adder gate circuits 10 and 12 are provided, and as the second adder gate circuit composed of one two-input AND gate 1003 and one two-input EX-OR gate 1004, adder gate circuits 11 and 13 are provided. Further, a carry select circuit 14 composed of an AND gate 141 and an OR gate 142 is provided, and selectors 15 and 16 are provided. In such a case, this device is formed to execute the addition of 2 bits and even when more than 2 bits are added, however, the addition can be similarly executed by extending the device. Thus, the circuit scale can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a carry selection addition circuit, and more particularly to a carry selection addition circuit that performs carry selection addition in n-bit digital addition.

[Conventional technology]

A conventional carry selection addition circuit of this type will be explained with reference to FIG.

FIG. 2 shows, as an example, a circuit diagram of a carry selection addition circuit which extracts 2 bits in n-bit addition. This circuit includes full adder circuits 22 and 23 that add the first bit of two bits, full adder circuits 20 and 21 that add the second most significant bit, a carry selection circuit 24, and a selector 25.
and 26. A first example and a second example of the full adder circuit shown in FIG. 2 are shown in FIGS. 3 and 4, respectively.

Figure 3 shows NAND games) 2001-2003 and EX-O
R (exclusive OR) gates 2004 and 2005 are combined, and FIG. Then, a carry signal Co to the upper digit is obtained.

The full adder circuits 20 and 22 in FIG. 2 are full adder circuits that output the addition result when there is a carry from the lower bit, and input the input signals A1 and AO as the summands and the input signals as the addend. It receives signals Bl and BO, and inputs logic rlJ to carry input terminals 215 and 217 as respective carry signals.

Further, the full adder circuits 21 and 23 are full adder circuits that output the addition result when there is no carry from the lower order, and logic "0" is input to each carry input terminal 216, 218.

Input signals to be added 201, 202 and 203° 204
are respectively input to full adder circuits 20.21 and 22.23 and added. In the addition of the first bit, when the carry signal CI from the lower bit is input to the carry input terminal 205, the selector 26 outputs the addition output signal 211 of the full adder circuit 22 to the output terminal 207.

If the carry signal from the lower bit is not input to the carry input terminal 205, the selector 26 selects the full adder circuit 2.
A summed output signal 213 of 3 is output from the output terminal 207.

The carry selection circuit 24 outputs the carry output signal 21 to the second bit.
This circuit outputs 4, and consists of an AND gate 241 and an OR gate 242, and its operation is performed when a carry occurs in the carry output signal 212 of the full adder circuit 23, and when a carry occurs in the carry output signal 212 of the full adder circuit 23.
When a carry occurs in the carry output signal 210 and a carry occurs in the carry input signal 205, a carry output signal 214 is output.

In the addition of the second bit, when the carry output signal 214 is input, the selector 25 outputs the addition output signal 208 of the full adder circuit 20 to the output terminal 206, and the carry output signal 2
14 is not input, the selector 25 outputs the addition specific power signal 209 of the full adder circuit 21 to the output terminal 206.

[Problem to be solved by the invention]

The full adder circuit used in the conventional carry selection adder circuit described above has three 2-input NOR gates and two
Since it is composed of two input EX-OR gates, it has the disadvantage that the circuit scale becomes large. Furthermore, since the maximum propagation path of the signal input to the full adder circuit must pass through three stages of gates, there is a drawback that the delay time becomes large. Further, a full adder circuit having another circuit configuration shown in FIG. 4 also has the same drawbacks as that shown in FIG. 3.

[Means to solve the problem]

The carry selection addition circuit of the present invention has n
The EX-NOR gate is equipped with one OR gate and an EX-NOR gate that receive two inputs of the summand and addend of each bit position of the bit data. n first gates that output the added value and output a carry signal for the upper bit from the OR gate;
an addition gate circuit, one AND gate that receives two inputs of the summand and the addend of each bit position, and an EX-OR
The EX-OR gate outputs an added value when there is no carry signal, and the AND gate outputs an added value when there is no carry signal from the lower bits.
A carry signal is generated from the ND gate to n second addition gate circuits that output a carry signal for the upper bit, and an AND gate of the second addition gate circuit, or a carry signal is generated from the lower bit. and at least one carry selection circuit that selects a carry in the upper bit in any case where the carry signal from the OR gate of the first addition gate circuit is desired to be generated simultaneously; and the first bit for each bit position.
The addition value output from the EX-NOR gate of the addition gate circuit is selected and outputted, and when there is no carry signal from the lower bit, the EX-OR of the second addition gate is performed for each bit position.
and n selectors that output the added value output from the gate.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a circuit diagram of an embodiment of the carry selection circuit of the present invention. The embodiment shown in FIG. 1 shows, as an example, a 2-bit carry selection adder circuit extracted from an n-bit adder circuit. This circuit consists of a 2-input OR game) 1001 and a 2-input EX-NOR exclusive negative OR game) 10
02 Addition gate circuit 10.12 as a first addition gate circuit composed of one 2-input AND gate 1003 and 2-input EX-OR gate 10041
The addition gate circuit 11.13 as a second addition gate circuit constituted by a number of circuits, a carry selection circuit 14 consisting of an AND gate 141 and an OR gate 142, and a selector 15.16.

The addition gate circuit 10.12 outputs the addition result when there is a carry from the lower order. In addition, addition gate circuit 1
1.13 outputs the addition result when there is no carry from the lower order.

Input signals to be added 101, 102 and 103° 104
are the addition gate circuits 10.11 and 12.1, respectively.
3 and is added. Here input signals 101, 10
3 is the summand A1 and AO.

Input signals 102, 104 are addends B1 and BO.

In the addition of the first bit, when a carry signal from the lower bit is input to the carry input terminal 105, the selector 16 outputs the addition output signal 111 of the addition gate circuit 12 to the output terminal 107.

If the carry signal from the lower bit is not input to the carry input terminal 105, the selector 16 outputs the addition output signal 113 of the addition gate circuit 13 from the output terminal 107.

The carry selection circuit 14 outputs the carry output signal 11 to the second bit.
This circuit outputs 4, but its operation is performed when a carry occurs in the carry output signal 112 of the addition gate circuit 13, and when a carry occurs in the carry output signal 110 of the addition gate circuit 12 and when there is a carry. When a carry occurs in the input signal 105, a carry output signal 114 is output.

In the addition of the second bit, when the carry output signal 114 is input, the selector 15 outputs the addition output signal 10B of the addition gate circuit 10 to the output terminal 106, and when the carry output signal 114 is not input, The selector 15 selects the addition 8 output signal 109 of the addition gate circuit 11 from the output terminal 10.
6 is output.

In this embodiment, the case where 2-bit addition is performed has been described, but it is clear that expansion can be similarly carried out when performing addition of 8 or more bits.

〔Effect of the invention〕

As described above, the present invention has the effect of significantly reducing the circuit scale by replacing the full adder circuit used in the conventional carry selection adder circuit with an adder gate circuit.

Furthermore, the maximum signal propagation path is reduced to one stage of gate circuits, compared to three stages of gate circuits in the conventional full adder circuit, which has the effect of significantly reducing delay time.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of an embodiment of the carry selection addition circuit of the present invention, FIG. 2 is a circuit diagram of a conventional carry selection addition circuit, and FIG. 3 is an example of the full addition circuit of FIG. 2. FIG. 4 is a circuit diagram showing a second example of the full adder circuit in FIG. 2. 10-13... Addition gate circuit, 14...
... digit selection circuit, 15, 16... selector,
20-23... Full adder circuit, 24...
Digit selection circuit, 25.26...Selector, 10
01...OR gate, i 002.・・・・・・
Exclusive negative OR (EX-NOR) gate, 1003
...AND gate, 1004...Exclusive OR (EX-OR) gate, 141...A
ND gate, 142...OR gate.

Claims (1)

[Claims] It has one OR gate and an EX-NOR gate that receive two inputs, the summand and addend of each bit of the n-bit data to be digitally added. n first addition gate circuits that output the added value in a certain case and output a carry signal for the upper bit from the OR gate; The EX-OR gate outputs an added value when there is no carry, and the EX-OR gate outputs an added value when there is no carry.
n second addition gate circuits that output an added value when there is no carry signal from the lower bits from the gate, and output a carry signal for the higher bits from the AND gate; and the second addition gate. A carry occurs in the upper bit when either a carry signal is generated at the AND gate of the circuit or a carry signal from the lower bit and a carry signal from the OR gate of the first addition gate circuit are generated simultaneously. EX-NOR of at least one carry selection circuit that selects and executes a
n selectors that selectively output the added value output by the gate and output the added value outputted by the EX-OR gate of the second addition gate for each bit position when there is no carry signal from the lower bits; A carry selection addition circuit comprising: