JPH03250226A - Watchdog timer - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a watchdog timer that determines the operating state of an electric circuit having a clock oscillation circuit.

[Prior Art] Recent electronic circuits use time standards and signal processing.
In addition, many devices have built-in clock circuits to maintain timing with other devices. A watchdog timer is used as a method to monitor whether these electronic circuits are operating normally.

FIG. 2 is a block diagram of a conventional watchdog timer. In the figure, 201 is a CPU, 202 is a watchdog timer, 203 is a crystal oscillator, and 204 is a CPU.
A clock signal output from U 201, and 205
is a reset signal output from the watchdog timer 202.

The watchdog timer 202 runs on the CPU 2 (II
It monitors the clock signal 204 output from the controller, and does not output a reset signal while the clock signal 204 with the period set in the normal state is input.

The clock signal 204 may be damaged due to runaway of the CPU 201, etc.
When no longer input, the watchdog timer 202 outputs a reset signal 205 to reset the CPU 201.

[Problems to be Solved by the Invention] Conventional watchdog timers 202 include those that use a mono multivibrator that uses the clock signal 204 as a trigger signal, and those that use a timer that uses the clock signal 204 as a reset signal. be.

However, in either case, it is possible to detect when the frequency of the clock signal 204 becomes lower than when it is normal, but it cannot be detected when the frequency of the clock signal 204 becomes higher than when it is normal. there were.

The present invention has been made to solve these problems, and provides a watchdog timer that can detect not only when the frequency of the clock signal is lower than normal but also when it is higher. The purpose is to

[Means for Solving the Problems] A watchdog timer according to the present invention includes a first clock oscillation circuit that outputs a first oscillation frequency f1, and a second clock oscillation circuit that outputs a second oscillation frequency f2. and,
A first frequency divider circuit that divides the first oscillation frequency f1 by 1/N1, a second frequency divider circuit that divides the first oscillation frequency f1 by 1/N2, and a second oscillation frequency f. The third frequency dividing circuit divides the second oscillation frequency f2 by 1/N3, and the fourth frequency dividing circuit divides the second oscillation frequency f2 by 1/N4. Furthermore, the output frequency f, /N of the first frequency divider circuit is used as a clock input, and the signal of the output wave number f2/N3 of the third frequency divider circuit is reset input, so that f /N /N5 < f2 The output frequency f2 of the 1N quinary counter and the fourth frequency divider circuit is set as /N3.
/N4 is used as a clock input, and a signal of frequency f1/N2 is reset input, and in normal state, t, , /N4/N, <
f1/N, , N road counter and N5
and a determination circuit that determines the presence or absence of an abnormality based on the output of the escape counter or the NB way counter. The fourth frequency dividing circuit may also be used as a third frequency dividing circuit.

Furthermore, the watchdog timer according to the present invention is a counter check circuit that detects the presence or absence of a change in the output of a flip-flop circuit before and after a reset signal is input to a plurality of flip-flop circuits constituting an N-ary counter or an N-6 counter. has.

This counter check circuit is an N5-ary counter or N
The hexadecimal counter has a D-type flip-flop circuit that inputs as a clock signal a signal whose phase is more advanced than the signal that resets the flip-flop circuit, and inputs the output from the flip-flop circuit to the data terminal, and this D-type flip-flop circuit. It consists of a NAND gate circuit which inputs the output of the circuit and the inverted output from the flip-flop circuit, and a D-type flip-flop circuit which inputs the output of this NAND gate circuit to a data terminal and inputs the reset signal to a clock terminal. There is.

[Function] In the present invention, if an abnormality occurs in the first oscillation circuit, the second oscillation circuit, or the first frequency dividing circuit to the third frequency dividing circuit, the output frequency thereof becomes higher than a predetermined value. If it becomes low or low, the N5 or N6 counter detects the abnormality.

Further, if an abnormality occurs in the operation of the N-ary counter or the N-6 counter itself, the counter check circuit detects it and notifies the abnormality.

[Example] An example of the present invention will be described based on the drawings. FIG. 1 is a block diagram of a watchdog timer according to an embodiment of the present invention. In the figure, 101 is a first clock oscillation circuit with an oscillation frequency of fi, and 102 is a first clock oscillation circuit with an oscillation frequency of f.
This is the second clock oscillation circuit of No. 2. 103 is fl 1
/N1 is a frequency dividing circuit, and 104 is a frequency dividing circuit that divides fl by 1/N.
This is a frequency dividing circuit that divides the frequency by two. 105 is a frequency dividing circuit that divides f2 by 1/N3, and 106 is a frequency dividing circuit that divides f2 by 1/N4. 107 uses a signal of frequency f1/N from the frequency divider circuit 103 as a clock input, and the frequency divider circuit 10
108 is an N 5-ary counter which receives the signal of frequency f2/N3 from frequency dividing circuit 106 as a reset input, and 108 receives the signal of frequency f2/N4 from frequency dividing circuit 106 as clock input, and receives the signal of frequency f1/N2 from frequency dividing circuit 104. This is an N hexadecimal counter that uses a signal as a reset input. 109 is the output signal 110 of the N5 counter 107 or the N6 counter 1
This is a determination circuit that determines the output signal 111 from 08.

Next, the operation of this watchdog timer will be explained.

The N-ary counter 107 counts the signal 1 with the frequency f/N1 as a clock input, and outputs the output signal 110 every time it counts N5, but during normal operation, f/N1/N < f/N
Since the N5-ary counter is reset with a signal of frequency f2/N35 2 3 such that the output signal 110 is not output.

Similarly, the N hexadecimal counter 108 has a frequency f2/N
4 is counted as a clock input, and the output signal 111 is output every time N6 is counted. During normal operation, f /N /N < f /
Since the N hexadecimal counter is reset with a signal having a frequency of 2 4 6 1 number f /N such that N2, the output signal 1]1 is not output.

Then, when neither the output signal 110 nor the output signal 111 is input, the determination circuit 109 determines that the circuit operation is normal.

For example, the first clock oscillation circuit 101 or the branch circuit 1
04 and the frequency f/N2 becomes low, the reset signal is not supplied to the N hexadecimal counter 108 at the predetermined timing, so the output signal 111 is output, and the judgment circuit 109 that receives this outputs the circuit operation. is judged to be abnormal. Similarly, if there is an abnormality in the second clock signal oscillation circuit 102 or the frequency dividing circuit 105, the frequency f
/If N3 becomes low, N5 decimal counter 107
An output signal 110 is output from the circuit, and the determination circuit 109 that receives this determines that the circuit operation is abnormal.

Also, the first clock oscillation circuit 1(]1 or the frequency dividing circuit 1
03 and the frequency f,/N becomes high, the N-5 counter 107 outputs an output signal 110, and upon receiving this, the determination circuit 109 determines that the circuit operation is abnormal. Similarly, if there is an abnormality in the second clock oscillation circuit 102 or the frequency dividing circuit 106, the frequency f
When 2/N4 becomes high, the N hexadecimal counter 108 outputs an output signal 111, and upon receiving this, the determination circuit 109 determines that the circuit operation is abnormal.

FIG. 3 is a circuit diagram showing details of the watchdog timer of FIG. 1. 101 and 102 are first and second clock oscillation circuits, respectively, and in this embodiment, the oscillation frequency is (fl-f2-32768 Hz). 302 is a frequency divider circuit which divides the 32768 Hz clock signal from the first clock oscillation circuit to 25
A clock signal 318 of 6 Hz, a clock signal 319 of 64 Hz, and a clock signal 317 having a higher frequency than the clock signals 318 and 319 are output.

103a is a frequency dividing circuit that divides the frequency of the input signal by 1/3;
Together with the frequency dividing circuit 302 in the previous stage, the frequency f, (-327
88 Hz) is divided by 1/384 (N, -384) and outputs a clock signal 314 (256/3 Hz). 104a is a frequency divider circuit that divides the input signal by 115, and together with the frequency divider circuit 302 in the previous stage, the frequency f2(-3
2768Hz) divided by 1/2580 (N2-2560)
and outputs a clock signal 315 (84/5 Hz). 105 is a frequency dividing circuit that divides the frequency of the input signal by 1/N3, and in this embodiment, it is also used as the frequency dividing circuit 10B.
N3-N4-1024, 327[18Hz glue O-/
The clock signal 31B is obtained by dividing the frequency of the signal by 1/1024.
(82Hz).

Note that the clock signal 317 is transmitted through the frequency dividing circuits 103 and 104.
.

Clock signal 314 315.3 in the differential circuit in 105
This is a clock signal for making each signal 16 into a narrow pulse.

Reference numeral 107 denotes an N-quinary counter, which is composed of D-type flip-flops 303, 304, and 305, and is a four-way counter (N5-4) that outputs 110 as an output signal. 306 is an OR gate, and when the system reset signal 301 or the clock signal 31B becomes rHJ, the D-type flip-flops 808, 304, and 305 are reset.

108 is an N hexadecimal counter, which is composed of D-type flip-flops 307, 308, and 309, and is a quaternary counter (N6-4) with 111 as an output.

310 is an OR gate, and system reset signal 30
1 or when the clock signal 315 becomes rHJ, the D-type flip-flops 307, 308, and 309 are reset.

109 is a determination circuit, which includes a D-type flip-flop 311
, , 312 and a NOR gate 313, and when the output signal 110 or 111 changes from rHJ to rLJ, the output 324 becomes rLJ.

Next, the operation of this embodiment will be explained.

FIG. 4 is a timing chart showing normal operation.

First, all circuits are reset by the system reset signal 301. The quaternary counter 107 counts the clock signal 314 (256/3 Hz), but under normal conditions, f /N1/N5 -82788/384 74 Hz' = 21-3
Hz< f2/Ns-32788/1
024-32Hz, and is reset by the clock signal 316 before counting 4, so the output signal 110 remains rHJ.

On the other hand, the quaternary counter 108 receives the clock signal 31B (3
2Hz), but under normal conditions, f
/N4 /N6-32768 /1024/4Hz
-8Hz<fl/N 2-32788/25
80-12-8Hz, and is reset by the clock signal 315 before counting 4, so the output signal 111
remains rHJ.

Therefore, the output signal 324 of the determination circuit 109 is held at rHJ.

FIG. 5 is a timing chart showing the operation when the first clock oscillation circuit 101 generates harmonic oscillation. When the first clock oscillation circuit 101 generates harmonic oscillation and the oscillation frequency f1 becomes 85536 Hz, which is twice the normal frequency, t, /N1/N3-85536 /384 /
4Hz';42.7Hz> f2/N3-32768
/1024=32Hz, so the quaternary counter 107 counts 4 before being reset by the clock signal 31B, so the output signal 110 changes from rHJ to rLJ.
This is latched by the D-type flip-flop circuit ALL, and the output 324 of the determination circuit 1 (19) becomes rLJ, so it is possible to detect that there is an abnormality in the circuit.

In exactly the same way, due to another reason such as the oscillation frequency of the second clock oscillation circuit 102 becoming lower, f /N
Even when /N > f /N3, an abnormality in the 152 circuit can be detected.

In FIG. 6, the second clock oscillation circuit 102 generates harmonic oscillation, and the oscillation frequency f2 is 85538 Hz, which is twice the normal frequency.
12 is a timing chart showing the operation when the following occurs.

In this case, f2/N4/N6-85536 /10
24/4)1z=16)1z> f , /N2-32
768/2580-12.8Hz, the quaternary counter lO8 counts 4 before being reset by the clock signal 315, so the output signal 111 changes from rHJ to rLJ, which is the D-type flip-flop circuit 31.
2, and the output 324 of the determination circuit 109 is rLJ.
Therefore, it is possible to detect that there is an abnormality in the circuit.

In exactly the same way, f /N4/N is caused by another reason such as the oscillation frequency of the first clock oscillation circuit 101 becoming slower.
An abnormality can also be detected when 6>f1/N2.

7 and 8 are circuit diagrams of a watchdog timer according to another embodiment of the present invention, in which FIG. 7 shows a frequency dividing circuit section and FIG. 8 shows an abnormality judgment processing section. In this embodiment, a function for checking the operation of the N5-ary counter 107, the N6-ary counter 108, and the output stage is added to the embodiment shown in FIG.

In FIG. 7, 701 is a frequency dividing circuit that divides the input signal by 115, and includes D-type flip-flop circuits 731 to 73.
6 and Noah gates 737 to 739. A clock signal 711 with a frequency of 84 Hz and a clock signal 712 with a frequency of 8 kHz are input to this frequency dividing circuit 107, and the clock signal 711 with a frequency of 64 Hz is
A clock signal 716 whose frequency is divided by 5 and whose phase is slightly shifted,
717 is output. 702 is a frequency dividing circuit that divides the input signal by 1z3, and D-type flip-flop circuits 740 to 7
42 and Noah gates 743° and 744. This frequency dividing circuit 702 inputs a clock signal 713 with a frequency of 2564 Hz, divides the frequency by 1z3, and outputs a clock signal 718 with a frequency of 84 Hz.

70B is a shift circuit, which is composed of D-type flip-flop circuits 745, 746 and NOR gates 747-749. This shift circuit 703 receives a 32 Hz clock signal 714 and outputs clock signals 719 and 720 whose phases are slightly shifted.

By the way, the clock signals 711, 712, and 713 are signals obtained by dividing the output of the first clock oscillation circuit 101 in FIG. 3, and the clock signal 714 is obtained by dividing the output of the second clock oscillation circuit 102. The process of generating these clock signals 711 to 714 will be omitted. The first clock oscillation circuit 101 and the second clock oscillation circuit 102 are different CPUs.
shall be built in. For example, the first clock oscillation circuit 101, the frequency dividing circuit (not shown) that generates the clock signals 711 to 714, and the circuits in FIGS. 7 and 8 are built in the first CPU side, and the second clock oscillation circuit It is assumed that the circuit 102 and the circuits that generate the clock signal 714 and signal 715 are built into the second CPU. The signal 851 is a reset signal, which is output from the CPU incorporating the second oscillation circuit 1 (12) as described above, and resets the D-type flip-flop circuits of the circuits 701 to 703 described above.

In Figure 8, 801 and 802 are N5 decimal counters 1
This is a gate circuit for reset signals of the D-type flip-flop circuits 303 to 305 of No. 07. 803 and 804 are N6
D-type flip-flop circuit 307 of advance counter 108
This is a gate circuit for the reset signal of ~309.

A counter check circuit 810 checks the operation of the N5-ary counter 107, and is composed of D-type flip-flop circuits 811, 812 and gate circuits 813-815. A counter check circuit 820 checks the operation of the N hexadecimal counter 108, and is composed of D-type flip-flop circuits 821, 822 and gate circuits 823-825.

Reference numeral 830 denotes a determination circuit, which includes, in addition to the D-type flip-flop circuits 311 and 312 shown in FIG.
33-835. 840 is a gate circuit;
40 is an output stage check circuit. This output stage check circuit 840 is composed of a D-type flip-flop circuit 842 and gate circuits 843-845.

846 is a gate circuit provided on the output side of the output stage check circuit 840. 851 is a detection signal taken into the first CPU, and 852 is a detection signal sent to the second CPU.

Next, the operation of this embodiment will be explained. Note that the operation of abnormality detection due to variations in the frequency of various clock signals is the same as the operation shown in FIG. 3, and the explanation thereof will be omitted here.

FIG. 9 is a timing chart showing the operation of the clock signal of FIG. 7 and the counter check circuit 820 of FIG. 8. Clock signal 714, 719.720713
, 718, 711, 716, and 717 are respectively inputted at the timings shown in the figure. For example, the D-type flip-flop circuit 307 of the N hexadecimal counter 108 inputs the clock signal 718 as a clock signal, and the output signal 322 is inputted to the D-type flip-flop circuit 307. It is input to circuit 308 as a clock signal. D type flip-flop circuit 30
The output signal 323 of 8 is input as a clock signal to the D-type flip-flop circuit 309 of the next stage, and is also input to the D-type flip-flop circuit 821 of the counter check circuit 820.
The inverted signal of the output signal 323 is input to the gate circuit 825.

When the clock signal 719 is input as a clock signal to the D-type flip-flop circuit 821 while the output signal 323 is in the rHJ state, the output signal 865 rises and becomes rHJ.
become. When the clock signal 720 is input to the reset terminal of the D-type flip-flip circuit 308, the output signal 323 is input to the falling gate circuit 825.

A signal 865 (rHJ) and a signal 323 (rLJ) are input to the gate circuit 825, and its output signal 866 becomes L. This output signal 866 is input to the D-type flip-flop circuit 822 as a clock signal. At this time, the clock signal 720 is also input to the clock terminal of the D-type flip-flop circuit 822, so the output signal 867 of this circuit 822 remains rLJ.

That is, when the output of the p-type flip-flop circuit 30B changes before and after it is reset, the output signal 867 of the D-type flip-flop circuit 822 remains rLJ, indicating that the N hexadecimal counter 108 is operating normally. I understand.

The output signal 867 of the D-type flip-flop circuit 822 is D
The output signal (here "L") is latched by a type flip-flop circuit 823 and sent to gate circuits 834 and 835.
There are no abnormalities in other circuits, and the output signals of D-type flip-flop circuits 311, 31.2, and 831 are L.
At the level, the output signal 870 of the gate circuit 835
becomes L level, and the first C
A detection signal 851 (here "H") is sent to the PU.

In the output stage abnormality detection circuit 841, the gate circuit 844 manually inputs the output signal 870 of the gate circuit 835, inputs its inverted signal to the data terminal of the D-type flip-flop circuit 842, and transmits the clock signal 714 to the clock signal terminal. manually, and the output is sent to gate circuits 844 and 845.
Enter. Then, the output of the gate circuit 845 is detected via the gate circuit 846 and sent to the second CPU as a signal 852.
When taken out as , it repeats on and off in synchronization with signal 714 during normal operation.

If there is an abnormality in the output stage abnormality detection circuit 841, its output signal will take either H or L value, and from this it can be determined that an abnormality has occurred.

By the way, if the output signal 323 of the D-type flip-flop circuit 308 does not change from rHJ to rLJ when the reset signal is input to the N-hex counter 108, the following operation occurs. When the output signal 323 is rHJ, the clock signal 719 is output to the D-type flip-flop circuit 82.
1, the output signal 865 rises and becomes rHJ. When the clock signal 720 is input to the reset terminal of the D-type flip-flop circuit 821, the output signal 323 should fall but does not fall. Signal 323(r
LJ) remains input and its output signal 866 remains rHJ, and this output signal 866 is input to the D-type flip-flop circuit 822 as a clock signal. At this time, the clock signal 720 is transmitted to the D-type flip-flop circuit 822.
Since it is also input to the clock terminal of the circuit 822, the output signal 867 of this circuit 822 becomes rHJ. That is, if the output of the D-type flip-flop circuit 308 does not change before and after it is reset, the D-type flip-flop circuit 82
The output signal 887 of No. 2 becomes rHJ, indicating that the N-hex counter 108 is not operating normally.

The output signal 867 of the D-type flip-flop circuit 822 is D
The output signal (here "H") is latched by a type flip-flop circuit 823 and sent to gate circuits 834 and 835.
There are no abnormalities in other circuits, and the output signals of D-type flip-flop circuits 311, 812, and 831 are rL.
Even at the time of J, the output signal 870 of the gate circuit 835 becomes H level, and the output signal 870 of the gate circuit 835 goes to the first CP through the gate circuit 840.
An rHJ detection signal 851 is sent to U.

FIG. 10 is a timing chart showing the operation of counter check circuit 810.

The operation of the counter check circuit 810 is the same as that of the above-mentioned counter check circuit 820, and the output signal 321 of the D-type flip-flop circuit 304 is input as a clock signal to the D-type flip-flop circuit 305 in the next stage, and the counter check circuit 810 is input to the data terminal of the D-type flip-flop circuit 811, and the output signal 3
The inverted signal of 21 is input to the gate circuit 815. When the clock signal 71B is input to the clock terminal of the D-type flip-flop circuit 811 while the output signal 321 is in the rHJ state, the output signal 861 rises and becomes rHJ. When the clock signal 717 is input to the reset terminal of the D-type flip-flop circuit 811, the output signal 321
is input to the falling gate circuit 815. The gate circuit 815 has an output signal 861 (rHJ) and an output signal 32.
1 (rLJ) is input, its output signal 866 becomes rLJ, and this output signal 862 is input as a clock signal of the D-type flip-flop circuit 812.

At this time, the clock signal 717 is also input to the clock terminal of the D-type flip-flop circuit 812, so this circuit 8
The output signal 867 of No. 12 remains rLJ, indicating that the N5-ary counter 107 is operating normally.

However, if the output signal 321 of the D-type flip-flop circuit 304 does not change from rHJ to rLJ when the reset signal is input from the N-quintal counter 107, the gate circuit 815 receives the output signal 861 (rHJ
) and output signal 321 (rLJ) remain input, and its output signal 861 also remains rHJ, and this output signal 862 is input as a clock signal to the D-type flip-flop circuit 812. At this time, clock signal 7
17 is also input to the clock terminal of the D-type flip-flop circuit 812, so the output signal 863 of this circuit 812 becomes rHJ. This shows that the N5-ary counter 108 is not operating normally.

[Effects of the Invention] As explained above, according to the present invention, even if the frequency of the divided clock signal increases or decreases as a result of some abnormality occurring in the clock oscillation circuit, it is detected as an abnormality. It is possible to do so. Moreover, by using two clock signal oscillation circuits, mutual confirmation is possible, and since the operation itself of the circuit for detecting abnormal operation is also checked, safety is further improved. Therefore, it is particularly suitable for fields that require high reliability and self-diagnosis functions, such as control circuits for medical injectors, measuring instruments, security equipment, etc.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a watchdog timer according to an embodiment of the present invention, FIG. 2 is a block diagram of a conventional watchdog timer, and FIG. 3 is a block diagram showing details of the embodiment of FIG. 4, 5, and 6 are timing charts showing the operation of the watchdog timer in FIG. 3; FIGS. 7 and 8 are block diagrams of watchdog timers according to other embodiments of the present invention; 9 and 10 are timing charts showing the operation of the embodiments of FIGS. 7 and 8. FIG. 101... First clock oscillation circuit, 102... Second clock oscillation circuit, 103... First frequency dividing circuit,
104...Second frequency divider circuit, 105...Third frequency divider circuit, 1013...Fourth frequency divider circuit, 107...N
Pentadecimal counter 108...N hexadecimal counter, 109
...Judgment circuit, 810°820...Counter check circuit.

Claims (6)

[Claims] (1) A first clock oscillation circuit that outputs a first oscillation frequency f_1, a second clock oscillation circuit that outputs a second oscillation frequency f_2, and divides the first oscillation frequency f_1 by 1/N_1. a first frequency divider circuit, a second frequency divider circuit that divides the first oscillation frequency f_1 by 1/N_2, and a third frequency divider circuit that divides the second oscillation frequency f_2 by 1/N_3; A fourth frequency divider circuit that divides the second oscillation frequency f_2 by 1/N_4; the output frequency f_1/N_1 of the first frequency divider circuit is used as a clock input; and the output frequency f_2/N_3 of the third frequency divider circuit;
Reset signal is input, and f_1/N_ in normal state.
An N_quinary counter set as 1/N_5<f_2/N_3 and the output frequency f_2/N_4 of the fourth frequency divider circuit are used as clock inputs, and a signal of frequency f_1/N_2 is input as a reset input. N_4/N_6<f_1/
N_hex counter set as N_2 and the N_
A watchdog timer comprising: a determination circuit that determines the presence or absence of an abnormality based on the output of the quinary counter or the N_hexadecimal counter. (2) The watchdog timer according to claim 1, wherein the fourth frequency dividing circuit is also used as the third frequency dividing circuit. (3) The counter check circuit according to claim 1, further comprising a counter check circuit that detects the presence or absence of a change in the output of the flip-flop circuit before and after a reset signal is input to the plurality of flip-flop circuits constituting the N_quintal counter. watchdog timer. (4) The counter check circuit inputs as a clock signal a signal whose phase is advanced from the signal for resetting the flip-flop circuit of the N_quintal counter, and inputs the output from the flip-flop circuit to the data terminal.
a NAND gate circuit which inputs the output of the first D-type flip-flop circuit and the inverted output from the flip-flop circuit; the output of this NAND gate circuit is input to the data terminal, and the reset signal is inputted to the 4. The watchdog timer according to claim 3, further comprising a second D-type flip-flop circuit input to the clock terminal. (5) The counter check circuit according to claim 1, further comprising a counter check circuit that detects the presence or absence of a change in the output of the flip-flop circuit before and after a reset signal is input to the plurality of flip-flop circuits constituting the N_hex counter. watchdog timer. (6) The counter check circuit inputs as a clock signal a signal whose phase is advanced from the signal for resetting the flip-flop circuit of the N_hex counter, and inputs the output from the flip-flop circuit to the data terminal.
type flip-flop circuit, a NAND gate circuit which inputs the output of this third D-type flip-flop circuit and the inverted output from the flip-flop circuit, the output of this NAND gate circuit is inputted to the data terminal, and the reset signal is inputted. 5. The watchdog timer according to claim 4, further comprising a fourth D-type flip-flop circuit input to the clock terminal.