JPH03250231A - Storage device - Google Patents

Abstract

PURPOSE:To realize LSI proper in performance, number of pins, gate scale and power by realizing the LSI with data width for a certain unit. CONSTITUTION:A memory control part (1) receives an interface address 1 signal 101 from an interface address signal 100, interface data 1 signal 201 of 4 bytes from an interface data signal 200 with 4X(m) byte width, and an interface memory control 1 signal 300 from an interface memory control signal 300. At such a time, a bank is positioned by a position 1 signal 701 and in the case of an operation to the single bank by decoding with the interface address signal 101, the data is read out to the memory part (1) and written. Therefore, a memory control 1 signal 501 is prepared. In the case of an operation (block transfer) to plural banks, the memory control 1 signal 501 is prepared to wait for the turn of the other bank and to read/write the data to the memory part (1). Thus, the LSI is suitably divided.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a storage device.

[Conventional technology]

Conventionally, the control section of this type of storage device was designed for each system because the memory interface, especially the clock and data width, differed from system to system.

Furthermore, as processors have become faster in recent years, the performance required of storage devices has also increased. However, since the rate of speed improvement of memory elements is slower than that of processors, methods have been taken to achieve high-speed data transfer by interleaving operations, block transfers, increasing data width, etc.

On the other hand, the use of LSI is progressing due to miniaturization due to high-speed data transfer and an increase in the amount of hardware. In the conventional technology, when implementing LSI, the size, number of bins, and power are only one L.
There are limits to what SI can achieve.

When performing high-speed block transfer using LSI, it is necessary to control the memory element by dividing it into multiple BANKs due to its performance, and if the number of bins increases or the data width increases accordingly,
This affected the number of bins, creating the problem of having to divide it into two or more.

[Problem to be solved by the invention]

The memory control unit of the conventional storage device described above is implemented in LSI by creating a memory control unit for each system, so it is difficult to divide the LSI appropriately considering the number of bins, gate size, power, etc. There is a drawback.

[Means to solve the problem]

The storage device of the present invention has one memory control unit that has a data width of a certain unit and can read and write data from the memory unit in response to a read request and a write request to the storage device, in a manner corresponding to the data width of the system. Alternatively, a plurality of them may be used, and one or more of the groups may be used to perform block transfer interleaving operations as one group.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram of one embodiment of the present invention. The memory control unit (1) 11 receives interface address signals 100 to interface address 1 signals 101 and 4.
The 4-byte interface data 1 signal 201 is received from the Xm byte wide interface data signal 200 and the interface memory control 1 signal 301 is obtained from the interface memory control signal 300.

At this time, the bank is located by the positron 1 signal 701, and if the operation is for a single bank by decoding with the interface write address signal 101, the memory unit (1) 2
Memory control 1 to read and write to 1
A signal 501 is created, and if the operation is to multiple banks (block transfer), a memory control 1 signal 501 is created in order to wait in line with other banks and read and write to the memory section (1) 21. do.

Further, in order to indicate that the memory request has been received, the memory control unit (1) 11 outputs an interface control signal 600 using the interface memory control signal 301 and the output of the interface control unit 30.
A signal is returned to signal 401.

Memory control unit (2)12. Memory control unit (n) 13
The memory controller (1) also operates in the same manner as the memory controller (1) 11.

FIG. 2 describes data signals.

When the data width is an interface with a width of 4Xm bytes,
The data is divided into m equal parts and one 4-byte is used as an interface.
Data 1, 2. ...Memory control is performed in units of 4 bytes using the m signal.

Furthermore, when controlling one batch of data by block transfer, which bank to perform the transfer operation with first is determined by the positive signal and the interface address signal.

That is, the bank to be controlled is determined by the position 1 signal.

mXj is the one that performs memory control using 4 bytes as shown above.
(=n) to make one storage device. However, this is just one example, and the memory control unit is not limited to 4 bytes.

〔Effect of the invention〕

As explained above, the present invention achieves improvements in performance, number of pins, and
It is possible to implement an LSI with appropriate gate scale and power, and by using a plurality of these in individual systems with different data widths, it is possible to match the performance of the processor.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is a time chart explaining the operation of FIG. 1. 11...Memory control unit (1), 12...Memory control unit (2), 13...Memory control unit (n), 21...
Memory II (1), 22...Memory part (2), 23.
...Memory unit (n), 3 (1...Interface control unit, 100...Interface address signal, 101
...Interface-address 1 signal, 102...
Interface address 2 signal, 103... Interface address n signal, 200... Interface fist data signal, 201... Interface urn data 1 signal, 202... Interface data 2 signal,
203...Interface data n signal, 300...
... Interface memory control signal, 301... Interface memory control 1 signal, 302... Interface memory control 2 signal, 303... Interface memory control n signal, 401... Interface control 1 signal, 402...Interface control 2 signal,
403...Interface control n signal, 501...
Memory control 1 signal, 502...Memory control 2 signal, 5
03...Memory control n signal, 600...Interface/control signal, 701...Posisilon 1 signal, 70
2... Posicilon 2 signal, 703... Posicilon en1
n signal.

Claims (1)

[Claims] Use one or more memory control units that have a certain unit data width and can read and write data from the memory unit in response to read and write requests to the storage device, in a manner that corresponds to the data width of the system. and means for using one or more groups so that a block transfer interleaving operation can be performed as one group.