JPH03250241A - Composite processor system - Google Patents

Abstract

PURPOSE:To efficiently control respective processors by providing a main memory, parallel processor equipped with a scalar processor, vector processor and plural data processing parts, and a processing control means to allocate the execution to each processor corresponding to the character of a data processing. CONSTITUTION:A main memory 5, a parallel processor 3 equipped with a scalar processor 1, vector processor 2 and plural data processing parts, and the processing control means to allocate the execution to each processor corresponding to the character of the data processing are provided. Therefore, the vector processor 2 and the parallel processor 3 simultaneously parallelly execute processings and by executing direct control through a path 15, however, a synchronous processing, etc., can be executed without interposing a master processor. Thus, time is shortened for the set-up processing and activation processing of the master processor and the both processors.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a composite processor system having a plurality of processors with different properties.

[Prior Art] A technique for efficiently controlling the processor elements of a parallel processor is known, as described in Japanese Patent Publication No. 145567/1982 entitled ``Very Large Computer''.

With this technology, each processor element, which all have the same processing function, can be efficiently controlled.

[Problems to be Solved by the Invention] By the way, data processing generally does not involve repeating similar processing.

When analyzing the locality of data processing, it can be classified into three types: first order.

1. The processing method and data change irregularly and have no characteristics, but the amount of calculation is not large.

2. The processing method is the same, but the data changes.

3. Both the processing method and data change irregularly, but if the processing is divided into sections of a certain size, there will be regularity in each division.

Which processors are suitable for processing these data?

They are skasi, vector, and parallel processors, respectively.
Each has different properties.

If we can create a means to control multiple types of processor systems by mixing processors that suit the local characteristics of data processing, we will be able to create a parallel processor system that dramatically improves the performance of current parallel processors. This will bring a completely new perspective to computational processing itself.

However, the conventional techniques described above cannot efficiently control processors having such different characteristics.

In addition, task switching and addressing are the most important technical issues in such a system that includes parallel processors as one of the system resources, but no adequate solutions have been found in conventional technologies such as the above-mentioned prior art. It has not been.

Therefore, in a system composed of a plurality of processors with different characteristics, the present invention realizes task switching of a resource including a plurality of data processing units inside the processor such as a parallel processor unit, and thereby enables multi-job processing. It is an object of the present invention to provide a multiprocessor system that can efficiently control each processor in multitasking processing, etc. [Means for Solving the Problems] To achieve the above object, the present invention provides a main memory.

Provided is a composite processor system characterized by having a parallel processor including a swash processor, a vector processor, and a plurality of data processing units, and processing management means that allocates execution to each processor according to the nature of data processing. do.

Note that desirably, the processing management means also performs allocation to each data processing unit.

Note that each data processing section of the parallel processor preferably has a local memory.

It is also desirable to have extended storage dedicated to parallel processors.

Further, in the multiprocessor system, it is preferable that any of the processors include the management means, and that the processing management means include an address conversion table and a storage protection mechanism for each processor.

Further, in the multiprocessor system, it is preferable that the processing management means has hardware capable of changing the value of a program counter of each data processing section of the parallel processor.

It is also desirable that each of the processors be provided with a buffer storage having a snooping function.

Further, it is preferable that a state management means for managing the state of each processor is provided, and the processing management means assigns execution to each processor according to the nature of the data processing and the state of each processor. Also, in this case,
It is preferable that the state management means manages the state of the parallel processor based on the state of the entire parallel processor and the state of each data processing section within the parallel processor.

[Function] According to the multiprocessor system according to the present invention, the processing management means assigns execution to each processor according to the nature of data processing, thereby controlling each processor in multi-job, multi-tasking processing, etc. Control efficiently.

In addition, when state management means is provided, the processing management means further improves the processing efficiency of the entire system by allocating execution to each processor according to the nature of data processing and the state of each processor. can be improved.

Further, in this case, the state management means manages the state of the parallel processor based on the state of the entire parallel processor and the state of each data processing section in the parallel processor, so that the processing management means directly handles the processing in the data processing section. can be managed up to the level of execution.

Furthermore, by providing any of the processors with the management means, the hardware configuration can be simplified,
Further, by providing the processing management means with an address conversion table for each processor and a memory protection mechanism, task switches can be managed in an integrated manner.

Further, in the multiprocessor system, the processing management means changes the value of the program counter of each data processing section of the parallel processor, thereby increasing the speed of processing assignment.

(Left below) [Embodiment] As an embodiment of the multiprocessor system according to the present invention, a multiprocessor system including a scalar, a vector, and a parallel processor having a plurality of data processing units will be described below.

First, a control method for each processor in this embodiment will be explained.

In general, data processing is not a uniform repetition of processing, but processing that is locally suited to a scalar processor, a vector processor, or a parallel processor.

Therefore, in this embodiment, data processing is divided into a plurality of segments, and a tag indicating the type of processor that most efficiently executes the segment is added to each segment.

The processor management unit of the multiprocessor system examines this tag and the status of each processor, and instructs the processor that is likely to perform the processing fastest at that time to execute the segment.

However, if task switching of parallel processors is impossible, the above process does not hold true. In a parallel processor system in which task switching is not possible, it is necessary to manage the parallel processor unit as a special resource, but in this case, it is difficult for such a system to execute jobs at high speed and in parallel.

Therefore, in this embodiment, the distribution of the data processing,
In order to realize task switching of parallel processors, the following software and hardware means are prepared.

1. When a program is logically divided and the divided parts are called segments, it is possible to generate a segment structure.
A programming language has a syntax that can describe the range of a segment structure, the characteristics of data processing described in a segment, etc. as a compiler directive J, and a compiler or interpreter that can decipher that syntax.

Note that the characteristics of data processing here refer to the logic in which data reference relationships are determined during program execution.
Instructions on what kind of object code or intermediate word to generate, how to process matrix operations most efficiently depending on the number of dimensions of the matrix, and what kind of object or intermediate word to convert to when different types of processors are used. Refers to instructions, etc.

In addition, the object code and intermediate language here include information for selecting a processor type. The information is not decoded by the processor, but is interpreted by the O8 or equivalent microcode or microprogram or hardware controlling the processor system.

2. A storage unit that indicates the status of each processor in a plurality of heterogeneous processor systems. The storage unit is a register, a type of flip-flop, or a specific area of main memory.

In this embodiment, the processor states include executing a task, waiting for an event, switching tasks, idling, and
Type 1 state expression is represented by 5 states of inoperability, a single state in which one type of task is executed, a composite state in which two or more types of tasks are executed, and an inoperable state in which tasks cannot be executed. These are two types of type 2 state expressions that are expressed in three states.

In the second type state representation, vector processors are either in a single state or in an inoperable state.

When in a single state, the first type state expression is one of four states: task execution, event waiting, task switching, and idle. When in an inoperable state, the first type state representation is inoperable. Waiting for an event includes what is called "interrupt factor pending."

In the second type state representation, a parallel processor takes three types of states: a single state, a composite state, and an inoperable state. Type 1 state representations are not applicable. However, the first type state is applied to each data processing section in the parallel processor section.

The following combinations of two types of state expressions are prohibited.

a. All data processing units cannot operate in single or combined state.

b. Any of the data processing units is not inoperable in the inoperable state.

All tasks are task-switching in the C1 complex state.

3. Means for identifying the task being executed in the data processing section of the parallel processor section. This is essential for realizing the second type state representation. This means is realized by information stored in a register or a specific area on the main memory.

4. Means for determining a processor to execute a segment based on the conditions requested in the first item and the status of the processor system shown in the second and third items.

Note that "to execute" here includes reservation of segment execution.

This means may be realized by software such as O8. This means is hereinafter referred to as a segment execution management program.

5. A processor that preferentially executes the management program of item 4 above. Hereinafter, this processor will be referred to as the master processor.

The following measures are not essential, but are necessary resources to ensure system performance.

6. Dedicated path for storing the contents of the data processing section in the parallel processor section to the storage section for task switching. The contents of the data processing unit include registers within the processing unit, program status words, control registers, and resources such as store-in buffer storage, vector registers, local memory, etc., if provided.

7. In a compiler or interpreter that encodes a program, means for processing a processor that executes (assumed to be) a generated segment as a logical processor. That is, means for converting a logical processor into a real processor, and means for converting interrupt exception processing generated from the real processor into a logical processor.

8. When the data processing unit in the parallel processor has sufficient local memory, means for dividing the local memory area into two or more areas and assigning each of them to a task.

That is, a protector such as a storage protection key for the divided areas or an access restriction bit on a relocation register, and means for displaying tasks being executed in each area.

9. A compiler or interpreter capable of generating object code or intermediate language for the second most suitable processor to execute the segment. Hereinafter, the second most suitable processor will be referred to as an alternative processor.

10. Means for indicating the start address of the alternative processor code.

Hereinafter, in order to simplify the explanation, in this example, 1. The mask processor is a scalar processor.

2. Includes the 6th to 9th means in the previous section.

3. Prepare the directive directives shown in Table 1 shown on the next page as compiler directives (a compiler or the like may automatically generate the contents of these directives).

shall be.

Table 1 Compiler directive statement number Syntax Function 1, $Seg+ment(na+ne, prior
ity-number, processor-name
, alternative-processor-na
me) Indicates the starting point, name, execution priority, and requesting processor name of the segment.

2, $Independent(X, Y)
This shows that there is no dependency in the data reference relationship between arrays X and Y.

3, $ Force (processor-nam
e)/$Forceend Converts the executable statement between the two statements into object code compatible with the processor specified by the processor name.

An overview of the operation of this embodiment will be explained below.

First, a user program is divided into a plurality of segments by the analysis function of a compiler or interpreter, or by instructions from the compiler directive.

The segment is given the name of the processor type suitable for its execution. This is called a tag below.

Segmentation is performed by a processor other than the vector processor, and the segmented object code is placed in main memory.

A management program on the master processor reads the tag of the segmented object code on the main memory, and then reads the storage section indicating the status of the plurality of processors.

If the requesting processor on the tag is a scalar or vector processor, and the first type state representation of the requesting processor is idle, the start address of the segment is sent to the processor and the processor is activated at the same time.

If the requesting processor's first type state representation is executing a task, waiting for an event, or switching tasks, execution of that segment is suspended, and when the requesting processor's first type state representation becomes idle, the beginning of the segment is The address is sent to the processor and the processor is activated at the same time.

Here, reservation means to move on to the process of determining the execution of a segment belonging to another task, but if the number of times the segment has been reserved is greater than a certain threshold, the processor requested by that segment is transferred to another task. Restrict its use for certain tasks.

If the requesting processor's type 1 state representation is inoperable,
Similar execution decisions are made for alternative processors. However, this is limited to cases where a vector processor is requested and a scalar processor is requested as an alternative.

In addition, if the requesting processor on the tag is a parallel processor and the type 2 state representation of the parallel processor is a single state, the data processing unit in the parallel processor unit is executing a task, and if it is idle, the task switch I do. The state transitions to task switching.

Then, after the task switch is completed, the data processing unit is assigned parallel processors to execute the segment that requested it.

If the data processing unit is inoperable while waiting for an event or during a task switch, the data processing unit will not be allocated at that timing.

Once a data processor is assigned to a segment requesting execution, the parallel processor transitions to a composite state unless it is in a single state and all data processors are idle.

When a data processing unit cannot be assigned to a segment requesting execution, that segment is placed on hold for execution.

If the second type state representation of the parallel processor that is the requesting processor is a composite state, the segment is suspended for execution.

In the case of inoperability, segment execution determination is made for the five alternative processors. In this case, only if you are requesting a parallel processor and requesting a space or vector processor as an alternative.

By the way, task switching of the data processing section of the parallel processor section is performed as follows.

First, when the local memory area is sufficiently larger than the area required by the execution requesting task, the local memory is divided into two or more areas and each area is allocated to a task.

At this time, a protector is activated to prevent processing of one task from destroying other task areas.

In other words, when a task is being executed in a certain area and the segment execution management program issues an instruction to transition to the task switch state, information such as registers in the data processing unit, program status words, control registers, etc. is saved to local memory. After that, the value of the pace register in the data processing unit is rewritten for the area of another task, and the information of the protector is replaced with that of the other task. Here, the other tasks are tasks to which the segment that is requesting execution by the segment execution management program belongs.

When the area of the local memory is smaller than the area required by the execution requesting task, information such as registers of the data processing unit, program status word, control register, etc. is written to the storage unit for task switching using a dedicated path. Similarly, the data processing unit's store-in buffer storage or local memory is similarly written to the task switch storage unit via a dedicated bus. The memory unit for task switching is a specific area of main memory or extended memory (Extend memory).
A high-speed storage medium such as ed-5torage is preferable.

However, even if such a high-speed storage medium is used, task switching of a large number of data processing units requires a considerable amount of time. In such a case, by staggering the transition timing of the data processing units to the task switch state using the management program, the processing of task 1 in the data processing units numbered 1 to i can be processed by the data processing unit numbered (i+1). In the switch processing, task 2 is processed in data processing units numbered (i+2) and onwards, and the tasks are sequentially switched.

Pipelining such task switching processing is called a switching pipeline.

Switching pipeline control works effectively when the segment requesting a parallel processor is an object code created with a logical data processing section in mind.

Hereinafter, details of an embodiment of the multiprocessor system according to the present invention will be described.

FIG. 1 shows the first processor of the composite processor system according to this embodiment.
The configuration is shown below.

In the figure, 1 is a space processor, 2 is a vector processor, 3 is a parallel processor, 4 is a storage control unit, 5 is a main storage unit, and 6 is an extended storage.

In this configuration, the master processor is a subprocessor.

As described above, in certain cases, the functions of the vector processor and the parallel processor are performed by the swash processor using the emulation function.

The compiler or interpreter is a skasi processor 1.
is executed.

A storage section indicating the state of the processor is provided within each processor.

The parallel processor 3 includes a plurality of data processing units therein, and includes a storage unit that indicates the status of the data processing units.

If cost reduction or high-speed task switching is not required, the above storage unit may be stored in the main memory 5.

The segment execution management program is executed on the master processor. The management program performs logical/real processor conversion, and tables necessary for this conversion are provided in the main memory.

The segment execution management program that allocates the execution of the segment is a local memory protector when the data processing unit in the parallel processor is equipped with a local memory and the local memory is divided and used by a plurality of tasks.

It also controls the display of running tasks.

Further, the segment execution management program also allocates the alternative processor.

In path 10.11, Sukasi processor 1 passes vector processor 2 through the segment execution management program. This is a path for checking the status of the parallel processor 3 and instructing startup or forced termination.

Paths 12 to 14 are paths through which the digital processor, vector processor, and parallel processor read and write data from the main memory 5, respectively. Path 15 is a path for direct control between the vector processor and the parallel processor.

An example of this direct control is schematically shown in FIG.

As shown in the figure, this example of direct control makes it possible to avoid competing processes and schedule processes.

In this way, the vector processor and the parallel processor execute processing in parallel at the same time, but by directly controlling them via the path 15, it is possible to perform synchronous processing etc. without going through the master processor. It is possible to reduce the time required for setup processing and startup processing of the processor and both processors.

The path 16 is a dedicated path used when the parallel processor 3 performs task switching.

Note that in the configuration shown in FIG.
However, if the extended storage 6 is used as storage exclusively for task switching, the path 16 may be directly connected to the extended storage 6.

A path 17 between the storage control unit 4 and the main memory 5 is provided corresponding to the bank configuration of the main memory.

Next, FIG. 2 shows the second and third configurations of the composite processor system according to this embodiment. In the figure, logical units and paths that are the same as those in FIG. 1 are indicated by the same numbers, and their explanations will be omitted.

In FIG. 2a, 7 is a buffer storage with soup function, and 19 and 20 are address and data buses, respectively.

Paths 17 and 18 are paths for reporting events occurring in the vector processor and parallel processor to the scat processor. Here, events include machine check interrupts in addition to end interrupts.

In the composite processor system shown in FIG. 2, the three data processing units of the parallel processors are composed of a square processor, a vector processor, or a square processor and a vector processor.

(Left below) Next, the segment execution management program will be explained.

FIG. 5 shows the structure of the segment execution management program.

The segment execution management program is composed of a logical/real processor conversion section, a storage management section, and a real processor activation section.

The memory management section consists of main memory management, local memory management, and extended memory management. Note that extended storage management is an option.

The logical/real processor management program selects a segment from the segment execution queue and determines the real processor that will execute it.

An outline of this operation is shown in FIG.

In the figure, if the state of the real processor is executable, then a.

If not possible, take route b.

If the real processor is a space processor or a vector processor, it is "executable" when its state is idle, and if it is a parallel processor, it is "executable" when it is in a single state. In other types 1.2 states, it is "unexecutable".

When the state of a processor is executable, a state storage unit that stores the state of each processor corresponding to that processor is set to execution.

If the state of a processor is non-executable, check the state of an alternate processor. If the status of the alternative processor is executable, the information in the status storage unit for that processor is set to executing. This process is indicated by a eroot in the figure. Routes a and a are different processes, but the only difference is the processor number, so they are omitted and shown as the same process.

After setting the processor status, check the processor status again.

Next, a logical/real processor conversion table is created and stored in main memory.

If the alternative processor is also not executable, the selected segment is returned to the wait queue.

As described above, after the logical/real processor conversion is performed and a real processor that executes the segment is allocated, the storage management section is then executed.

The storage management unit manages main memory and local memory separately.

If the real processor is a scalar or vector processor, local memory management is omitted.

FIG. 7 shows the processing procedure of the main memory management program.

As shown, when the segment is executed for the first time,
First, free space in main memory is checked.

If there is no free space, that segment cannot be executed, so the information in the processor state storage section and the logical/real processor conversion table are purged.

Also, the real processor assigned by the logical/real processor converter is released.

When a free area exists, the base address of the segment is determined (the base address is set to the starting address of the free area), and this address is written in a table on the main memory. Next, a table for the B register, which will be described later, is secured in the main memory and initialized. As will be described later, the segment base address on the local memory is set in the B register and used for address conversion.

Note that if a segment execution request is made on an area that has already been secured on the main memory, the main memory management process is skipped. Furthermore, whether or not a segment requires main memory reservation is the responsibility of the compiler or the like that generates the segment.

By the way, in this embodiment, segments are grouped into tasks, which are larger processing units, and tasks are further divided into
Manage each process by organizing it into jobs, which are larger processing units.

In this case, the same processing as shown in FIG. 7 is performed for tasks that are larger processing units than segments. However, in the case of a task, there is no processor allocation process shown in FIG. 6, and there is no need to purge the conversion table or the like.

If the segment execution processor is a parallel processor,
Furthermore, the local memory management program checks the free status of the local memory.

FIG. 8 shows an outline of the local memory management program.

As shown in the figure, if there is free space in the local memory, the direction of route a in the figure is taken.

If there is no free space, the parallel processor control unit that maintains the state of the parallel processors (see Fig. 3,
) is checked, and if it is a single state, it takes the C route, and if it is a composite state, it is registered in the segment waiting queue and the process ends.

Note that if route C is taken and the parallel processor system is transitioned to the task switch state, the parallel processors will transition from the single state to the composite state, and the task switch state will not occur twice. When the task switch process is completed,
The area occupied by the task evicted from local memory becomes free space and is allocated to the requested segment.

Thereafter, it merges with the C route, and the start address of the free area is set as the segment base address, and the logical address generated by the data processing unit is associated with the real segment base address of the local memory.

A table is created for the B registers of the parallel processors. That is, a local memory area is assigned.

Note that if there is sufficient free space in the local memory, a segment requests a parallel processor, and the parallel processor is in a single state, the local memory management program takes route a and does not transition to the task switch state.

However, the logic/real processor converter (see Figure 6)
Now, we will take route C, set the B register, interrupt the task being executed, and send the task containing the execution request segment to that processor (
(in this case limited to parallel processors).

At this time, the state of the processor changes from single to composite to single. In this case, the task switch time is much shorter than with a local memory management program.

If the local memory capacity can accommodate n task areas, n multiprocessing is virtually possible within the parallel processor. It is called pseudo because there is only one active task at a given moment.

Allocation to the actual data processing unit that executes segments on a parallel processor system is done by another resource.

As described above, after the real processor, main memory, and local memory are allocated, segment execution is directed to these resources. This instruction is given by the real processor starting section. The flow of the starting section is shown in FIG.

As shown in the figure, the real processor starting unit transmits the task number to be executed and the start address of the segment to be executed.

In addition, if the real processor is a parallel processor, before sending the start address, an A register table that associates the execution task number with the job base address of the main memory and the task base address of the local memory is stored in the A register. Write the previously created B register table to the B register.

In this embodiment, it is assumed that the instruction to be executed first by the activated real processor is stored in the start address area of the segment.

Furthermore, in this embodiment, as mentioned in part earlier, the execution and management of jobs and tasks is assumed to be performed by a functional unit higher than the segment execution management program.Therefore, the creation of the A register table The settings of the and A registers are performed by a higher-order functional unit prior to starting up the actual processor.

Next, parallel processors will be explained.

FIG. 3 shows the configuration of a parallel processor.

In the figure, 1 indicates a mask processor, and 3 indicates a parallel processor.

Only one parallel processor control unit 50 exists in the parallel processor and manages the states of a plurality of data processing units.

In the data processing unit 30, 54 is a local memory, 55 is a data processing unit, 56 is an operand address generation unit that generates an address for operand access, 52.5
3 is an access operation logic unit regarding operand data. A data processing unit 55 includes an instruction decoding section 106, an instruction address generation section 107 for generating an address for instruction access, an operation [131], and a general-purpose register 32.

A plurality of data processing units 30 are provided within the parallel processor 3.

FIG. 4a shows the configuration of an access operation logic section regarding operand data of a data processing section of a parallel processor.

In the figure, 50 is a parallel processor control unit, 54 is a local memory 555 is a data processing unit.

Only one control unit 50 exists in the parallel processor and manages the states of a plurality of data processing units.

51, 57, 58, 59, 60 are registers, 56 is an address adder, and 60 is a switch circuit. 52 and 53 are a register group consisting of multiple registers.3 As mentioned above, in this data processing device, segments are grouped into tasks, which are larger processing units, and tasks are further grouped into larger processing units. Manage each process by organizing it into a certain job.

The operation will be explained below.

As described above, first, the master processor, ie, the subprocessor, sends the contents of the A register table to the parallel processor control unit via the path 10, prior to activating the data processing unit. This content is set in the A register 52 through a path 82, and a conversion table between the task number and the base address of the task on the local memory and the job base address on the main memory is created.

Similarly, the scat processor sends the contents of the B register table to the parallel processor control unit via the path 10. This content is set in the B register 53 through path 82, and a conversion table between the logical address and the base address on the local memory of the segment is created.

Here, addressing of the data processing section of the parallel processor will be explained (see FIG. 4).

Since the address generated by the operand address generator is a logical address, it is necessary to convert it into a real address in the main memory and local memory.

Therefore, in order to reduce the amount of hardware for address translation logic, address relocation is performed for the main memory on a job-by-job basis, and on the local memory on a segment-by-segment basis.

Note that in this embodiment, the data processing unit and the operand address generation unit do not recognize tasks or jobs.

Further, the upper task number is assigned to job identification, and the lower task number is assigned to tasks classified by job.

A main memory access that occurs within the data processing unit constitutes the real address of the main memory from the job base address of the main memory 5, which is the upper data of the A register 52 determined by the task to be executed, and the logical address where the address adder was generated. This is done by

In addition, when a local memory access occurs in the data processing unit, the task base address of the local memory, which is the lower data of the A register 52 determined by the task to be executed, and the upper address of the logical address where the address adder has been generated are stored in the B register 53. This is done by constructing the real address of the local memory from the segment base address of the local memory 54 converted by the data of the part excluding the I bit, and the remaining lower address of the logical address.

Here, 1 bit of the B register 53 is set when the conversion table of the above-mentioned search processor is set.
Bit=11' indicates that the segment address is not on local memory. ■When the bit is '0',
The segment address field of the B register indicates the real address where the segment area on the local memory is located.

In addition, in Fig. 10, extended memory is added as an option,
One method of allocating storage areas when a dedicated path 16 for task switching is provided between a parallel processor and expanded storage is shown.

Calculations performed on a parallel processor are longer than those performed on a computer or vector processor, so
Control should be such that tasks executed on parallel processors and tasks executed on other processors may be different.

In order to realize such control and not make storage control too complicated, it is desirable to separate virtual storage using external storage such as main storage paging and that of the parallel processor section.

Therefore, we will discuss segment-based paging between local memory and expanded storage within a parallel processor, which is necessary to achieve this.

As shown in the figure, the E bit is added to the B register 53,
It is defined that when the E bit is 1', the segment space exists on the local memory and the C register is valid; when it is 0', the segment space exists on the extended memory and the C register is valid.

The segment address field of the B register 53 is set to indicate the column address of the C register.

There are two types of C registers, C, and C2, which hold segment addresses on local memory and addresses on expanded storage, respectively.

As a result, the logical address from the data processing unit is converted into a real address by referring to the B register and then the C register whose E bit indicates validity.

Further, when only one extended storage exists in a parallel processor system, it is desirable to further divide the extended storage space by the number of the data processing section. In this case, the number of the data processing unit is held in the p field of the C2 register 101 (see FIG. 10).

Note that the C□ and C2 registers may not be actual registers but may be tables on the local memory.

When the settings of the A register and the B register are completed, the mask processor activates the data processing section as described below, as described above.

The master processor (see FIG. 3) informs the parallel processors via the bus 10 of the number of the actual data processing unit to be activated and the task number to be processed by the data processing unit, that is, in this case, the main memory of the corresponding job. sends the base address above and the register number of the A register holding the base address in the task's local memory.

In response to this, the parallel processor control section 50 sends an activation signal and the number of the A register to the target data processing section via the bus 80.81. The register number is set in register 51.

Upon receiving the activation signal, the data processing unit 30 executes processing while accessing the main memory or local memory, and the access to the main memory or local memory is performed as follows according to the addressing described above.

The address generated by the opaland address generation unit 56 is a logical address. The upper and lower addresses are sent out on buses 83 and 84, respectively. Address relocation of the upper address is performed by the B register 53, and the converted address is set in the register 57. The lower address is set in register 58 via bus 84. The data on registers 57,58 indicate addresses within the segment.

The data on the register 51 indicates the register number of the A register 52, and the lower data of the A register is the start address of the task on the local memory.

The lower address of the A register is set in register 59, and registers 59, 57, and 58 constitute the real address on the local memory. The real address is sent on bus 85.

Store data sent from the data processing unit is sent on bus 86 for local memory accesses.

In the case of a command to read the local memory, the data processing unit 55 acts on the switching circuit 60 via the bus 88 and sends the output of the local memory onto the bus 87.

When the store data sent from the data processing unit 55 is accessing the main memory 5, the bus 86 sends out the door data to the main memory control unit 4 connected to the bus 14. On the other hand, the data processing unit 25 sends a '0' signal onto the bus 88. This is inverted by inverter 61 and sent onto path 89. The signal on path 89 is a command indicating that the data signal on path 14 is valid.

The address is transferred to the A register without relocation conversion.
It consists of a lower address on path 85, which is an address generated by the operand address generator that has passed through the B register, and an upper address indicating the base address of the job on register 62, and is sent out on path 90. In other words, in the case of main memory access, the task base address,
The real address of the main memory is constructed from the address generated by the operand address generation unit 84 and the job base address without converting the segment base address. This is because it is assumed that within the job in the main memory, the address and the logical address generated by the operand address generation unit 56 are equal.

In the case of an instruction that reads and compares the main memory, the data on path 14 is meaningless. The data processing unit 55 sends the type of access to the main memory 5 and the sync information necessary for successive main memory accesses over a path 91.

Using this sink information, data read from main memory is distributed to the real processor.

The details of this method will be omitted since it is a method adopted by a conventional parallel pipeline vector processor.

When the data processing unit is in the task switch state and receives an instruction from the master processor to send data from the local memory to the task switch storage section, address generation is performed in the same way as when reading from the local memory.

However, the signal value on path 88 is t Or, and the data read out by switching circuit 60 is on path 16.
(Store). Orders on path 91 are directed to main memory store.

After the task area of the local memory is written to the main memory or the task switch storage, other task areas are read from the main memory or the task switch storage and written to the local memory.

That is, when reading from the main memory, writing is done to the local memory via the path 14, and when reading from the task switch storage section, the dedicated path 16 (fetch
) is written to the local memory via the switching circuit 63.

Note that the switching circuit 60 is controlled by the data processing unit 55 according to the access destination included in the given command. In addition, a program that describes task switch processing is made to reside in a specific area of the local memory. Branching to this program is a type of task switching.

Next, the instruction decoding section 106 and instruction address generation section 107 of the data processing section 30 of the parallel processor will be explained.

When the data processing unit is instructed to start executing a segment or switch tasks from the master processor, it rewrites the program counter, sends the generated instruction address to main memory or local memory (including extended memory), fetches the instruction, and decodes it. The instruction decoding unit and instruction address generation take in and decode this instruction.

Note that in this embodiment, instructions are stored in a logical space different from the operand data described above.

Therefore, the access operation logic shown in FIG. 3 is not used for fetching instructions. However, when instructions and operand data are stored in the same logical space, the access operation logic shown in FIG. 3 may be shared in order to reduce the amount of hardware. Note that in this case, priority logic is required to control conflicts between operand data access and instruction fetch.

FIG. 11 shows the configuration of an instruction decode section and an instruction address generation section of a data processing section of a parallel processor.

In FIG. 11, paths 150-152 are command, order, and address data lines from the mask processor.

When the master processor is a scalar processor, path 11 shown in FIG. 1 corresponds to paths 150 to 152. On this path, the command signal is sent one cycle earlier than the address and order signals.

After the command signal on path 150 is latched by latch 105, it acts on register 106, and the order signal on path 151 is taken into the register.

When the order signal is '1', the generated address is sent to the main memory, and when it is '0', it is sent to the local memory side.

When a command instructing activation is sent on path 150, the output of address adder 107 is replaced by the address on path 152 by selector 108, and set in program counter 109. In the case of segment execution start or task switch, on path 152, as described above.

The start address of the segment to be executed is sent, and the instruction to be executed first by the data processing unit is stored.

The output of the program counter is added by the address adder 107 to the output of the register 110 storing the instruction word length, and an instruction address string is sequentially created.The generated instruction address is added to the register 10 by the switching circuit 111.
The data are sent to the main memory and local memory according to the order information of No. 6, respectively.

Instructions read from main memory and local memory pass 15
3. Passes 154. The signal to select re-memory is register 1.
12 on the selector 113 and sends the read data to the decoder 114.

The decoder 114 decodes the command and sends an order signal or the like to each resource such as a data processing unit in the data processing section and an operand address generation section via a path 155.

Thereafter, when the decoder detects the end of the segment, a signal is sent on path 160 to reset register 106. This signal ends the instruction of the mask processor.

Note that when the first type state of the data processing section changes, the decoder 114 sends a command and three types of order signals onto the paths 156 to 159, respectively.

(Hereinafter, blank space) Next, here, processors other than the data processing unit of the parallel processor and the parallel processor are provided.

The first type state management unit that manages the first type state will be explained.

FIG. 13 is a block diagram of the first type state management section.

In FIG. 13, the output of the AND circuit 300 corresponds to the triggers 250 to 2'80 in FIG. 12, which will be explained later.
The same number was assigned to the output of the AND circuit. register 200
The value of ~204 is '1' in the state of the same number in Figure 12,
Otherwise, it is '0'. The outputs of the registers 200-203 are ANDed by the AND circuit 301 with the signal values on the paths 250-280 and the inverse of the output of the register 204 to generate set and reset signals for the registers 200-203. Logic circuit 302 is an OR circuit.

When a machine check signal is sent on path 290, registers 200-203 are reset unconditionally and register 204 is set to Jl. register 204
will not be reset unless a reset signal is sent on path 291.

Registers 200-204 represent type 1 state representations of the processor.

When the processor is a parallel processor, registers 200 to 204 exist for each data processing unit within the processor. The register 303 also identifies the task currently being executed.

Although the value of the register 303 indicates the task number, it is meaningless unless the state of the data processing unit is executing a segment or waiting for an event.

The outputs of the registers 200 and 201 are logically summed by an OR circuit 307. The output '1' of the OR circuit 307 indicates whether the contents of the register 303 are significant or not, and acts on the selector 306. When the contents of register 303 are significant, pass 351
The task number on the top is 101 when it is meaningless.

The part below the dotted line 352 is the control section of the parallel processor system (
50) is a block diagram of the priority determination logic of FIG. 3; FIG. Line 353 indicates each data portion.

The flip-flop 320 indicates whether or not the data processing unit can accept a segment execution request.6 That is, it can be accepted when the output of the flip-flop is t Oj, and '1'.
It is not acceptable when . When a segment execution request is sent from the master processor to path 370, AND circuit 3
At 21, the output of the OR circuit 322 is ANDed. If even one of the plurality of data processing units can execute the segment, the signal value on path 371 is 11'. The signal on path 37 enables the output of priority circuit 323. The priority circuit selects any one of the flip-flops 320 with a value of '1' and outputs its serial number on path 372. This number is decoded by decoder 324 and sets a flip-flop. pass 37
3 is the east line. Also, the serial number is in register 325.
The master processor determines which data processing unit is to execute the segment.

Next, the type 2 state management section of the parallel processor control section 3 that manages the type 2 state of the data processing section in the parallel processor will be described. FIG. 14 shows its configuration.

The parallel processor control unit is a logic unit for converting the first type state representation of the data processing unit in the parallel processor into the second type state representation. In order to simplify the logic of the parallel processor control section, the conversion is performed by a program or microprogram within the mask processor. The parallel processor control unit is the logic for reading and comparing the data and status referenced by the program.

In FIG. 14, for the segment being executed in each data processing section, an identification number is written on the path 450.
1, the real processor number is sent from the master processor's logical/real conversion program. Information on the segments being executed in each data processing section is distributed by the switching circuit 400 according to the actual processor number.
It is set in register 401.

Paths 452, 453, and 454 are paths for propagating point signals from the master processor side to determine the segment identification number of the data processing section, whether it is in an idle state, and whether it is inoperable.

The segment identification number is meaningless when the data processing unit is idle or inactive. Whether the data processing section is in an idle state is indicated by whether the value of the register 405 is '1' or '10'.

Whether the data processing section is in a state in which machine check or other operations cannot be performed is determined by whether the value in the register 409 is '1' or 'OI.' The values in both registers are logically ANDed by an OR circuit 412, and a segment is added to the path 457. A signal is sent indicating whether the identification number is valid or invalid.

Signals indicating whether all data processing units are in an idle state or in an inoperable state are generated by AND circuits 406 and 410, respectively, and sent onto paths 458 and 459.

Based on the signals of paths 458 and 459, the mask processor determines the second type state representation of the parallel processor using the seventeenth type 2 state representation conversion program shown below.

FIG. 15 shows the flow of this first/second type state representation conversion program.

The first/second type state representation conversion program first begins with the path 45.
It is checked whether the signal value of 9 is 1, that is, whether all data processing units are in an inoperable state (step 1601), and if all data processing units are in an inoperable state, the second type state expression is is determined to be inoperable (step 1.60
2).

If the signal value on the path 459 is not 1, it is checked whether the signal value on the path 458 is 1, that is, whether all data processing units are in an idle state (step 1603), and all data processing units are in an idle state. If it is a state, the second type state expression is determined to be a single state (step 1604).

If the signal value of the path 458 is not 1, steps 1605 and 16 sequentially search for data processing units that are not in an idle state.
06, 1607 = 1608°1609.161o,
1611), (7) Read the segment being executed by the data processing unit Step 1, 612.1613)
, Then, steps 1614, 1615, 1616, 1617, 1618) to find another data processing unit that is not in an idle state, step 1620) to read the segment being executed by that data processing unit, and perform the data processing found earlier. It is checked whether or not the segment is executing the same segment as the segment being executed (step 1621), and if a different segment is being executed, the second type state expression is determined to be a composite state (step 1624).

If the data processing unit that was found earlier is executing the same segment as the segment that is being executed, the data processing unit that was found earlier is executing a segment that is different from the segment that is being executed. The maximum number of processing units is searched (step 1622), and if there is no data processing unit executing different segments, the second type state expression is determined to be a single state (step 1625).

Next, state transitions in the first type state representation will be explained.

FIG. 12 shows this state transition diagram.

In the figure, 200 is a segment being executed, 201 is holding an event, 202 is task switching, 203 is idling, and 204 is in an inoperable state.

Further, triggers for transitioning each state are shown by solid and dotted arrows.

Trigger number 250 is a signal on path 370 in FIG. 13, which is a command sent from the master processor to the data processing unit by the task startup routine executed by the master processor, and 251 is a signal on path 150 in FIG. 11. 260 is a task activation routine executed by the master processor, and 260 is assumed to be a command to instruct internal state saving or recovery, sent from the master processor to the data processing unit by a task switching routine executed by the master processor. The path 156 in FIG.
．． It is assumed that the signal on 157 is set,
261 is assumed to be caused by a signal sent onto buses 156 and 158 in FIG. 13 by an instruction at the end of an instruction stream executed by the data processing section.

270 indicates an external factor or interrupt, 280 indicates a completion signal from a resource within the processor, and 290 indicates a machine check signal.

As described above, according to this embodiment, the square, vector,
A multiprocessor system consisting of parallel processors can divide a job into segments and allocate the segments to the processors that can process them most efficiently.

Furthermore, this function allows each processor to operate with high efficiency when a large number of jobs with different properties must be processed, thereby improving job throughput.

In addition, the amount of hardware of the processor is in the order of parallel processor>vector processor>smart processor, and by operating each processor with high efficiency, it is possible to realize a computer with "high processing power with a small amount of material."

Furthermore, according to this embodiment, the processing of the parallel processor can be interrupted and the processing of other tasks can be executed, so that the parallel processor can be handled as a background processing resource. Furthermore, since large-capacity auxiliary storage such as extended storage can be used as storage for task switching of parallel processors, the local memory can be configured to be relatively small, and costs can be reduced.

Further, according to this embodiment, a plurality of types of segment execution request processors can be set. Thus, if the first candidate processor is busy or inoperable, the second candidate processor can execute. This function can be expected to improve processing efficiency and reliability.

[Effects of the Invention] As described above, according to the present invention, in a system composed of a plurality of processors with different characteristics, tasks of a resource including a plurality of data processing units inside a processor such as a parallel processor unit By realizing switching, it is possible to provide a composite processor system that can efficiently control each processor in multi-job, multi-tasking processing, etc.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of a composite processor system according to an embodiment of the present invention, FIG. 2 is a block diagram showing another configuration of the composite processor system according to an embodiment of the present invention, and FIG. Figure 4 is a block diagram showing the configuration of the parallel processor's operand access operation logic, Figure 5 is a flow diagram showing the processing procedure of the segment management program, and Figure 6 is the logical/real processor. 7 is a flowchart showing the processing procedure of the main memory management section, FIG. 8 is a flowchart showing the processing procedure of the local memory management section, and FIG. 9 is a flowchart showing the processing procedure of the real processor starting section. Flow diagram showing the processing procedure, No. 10
The figure is an explanatory diagram showing addressing when adding extended memory.
Figure 1 is a block diagram showing the configuration of the instruction decoder unit of the data processing unit of the parallel processor unit, Figure 12 is a state transition diagram based on the first type state representation of the processor, and Figure 13 shows the configuration of the processor state management logic unit. Block diagram, FIG. 14 is a block diagram showing the configuration of the type 2 state management section of the parallel processor, FIG. 15 is a flow diagram showing the processing procedure of the type 1/second state representation conversion program, and FIG. 16 is the processor FIG. 2 is an explanatory diagram showing synchronization processing between DESCRIPTION OF SYMBOLS 1... Scalar processor, 2... Vector processor, 3... Parallel processor, 5... Main memory, 50.
...Parallel processor control unit 50.30...Data processing unit, 54...Local memory, 55...Data processing unit, 56...Operand address generation unit, 5
2゜53...Access operation logic unit, 55 is a data processing unit, 106...Instruction decoding unit, 107...
This is an instruction address generation unit.

Claims (1)

[Claims] 1. A parallel processor including a main memory, a scalar processor, a vector processor, and a plurality of data processing units, and processing management means that allocates execution to each processor according to the nature of data processing; A composite processor system comprising: 2. The multiprocessor system according to claim 1, wherein each data processing section of the parallel processor has a local memory. 3. The multiprocessor system according to claim 1 or 2, further comprising an extended storage device dedicated to the parallel processors. 4. The multiprocessor system according to claim 1, 2 or 3, wherein any of the processors is provided with the management means, and the processing management means is provided with an address conversion table and a storage protection mechanism for each processor. A multiprocessor system featuring: 5. The multiprocessor system according to claim 1, 2, 3, or 4, comprising state management means for managing the state of each processor, wherein the processing management means is configured to control the nature of data processing and the state of each processor. 1. A multiprocessor system, comprising assigning execution to each processor accordingly. 6. The composite processor system according to claim 5,
The multiprocessor system is characterized in that the state management means manages the state of the parallel processor based on the state of the entire parallel processor and the state of each data processing unit within the parallel processor. 7. The multiprocessor system according to claim 1, 2, 3, 4, 5, or 6, wherein the processing management means includes hardware capable of changing the value of the program counter of each data processing unit of the parallel processor. A multiprocessor system featuring: 8. The composite processor system according to claim 1, 2, 3, 4, 5, 6, or 7, wherein each of the processors is provided with a buffer storage having a snooping function. .